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| 型号： | PF48F0P0ZTQ0 |
| 厂商： | Intel Corp. |
| 元件分类： | 圆形连接器 |
| 英文描述： | Circular Connector; Body Material:Aluminum; Series:PT00; No. of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Socket; Insert Arrangement:10-98 |
| 中文描述： | 英特尔StrataFlash嵌入式存储器 |
| 文件页数： | 49/102页 |
| 文件大小： | 1609K |
| 代理商： | PF48F0P0ZTQ0 |
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1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
49
9.1.2
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted.
During a write operation, address and data are latched on the rising edge of WE# or CE#,
whichever occurs first.
Table 20, “Command Bus Cycles” on page 50
shows the bus cycle
sequence for each of the supported device commands, while
Table 21, “Command Codes and
Definitions” on page 51
describes each command. See
Section 7.0, “AC Characteristics” on
page 33
for signal-timing details.
Note:
Write operations with invalid V
CC
and/or V
PP
voltages can produce spurious results and should not
be attempted.
9.1.3
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high
-
impedance
(High-Z) state, WAIT is also placed in High-Z.
9.1.4
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially reducing
power consumption. In standby, the data outputs are placed in High-Z, independent of the level
placed on OE#. Standby current, I
CCS
, is the average current measured over any 5 ms time interval,
5
μ
s after CE# is deasserted. During standby, average current is measured over the same time
interval 5
μ
s after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase operation, it
continues to consume active power until the program or erase operation is completed.
9.1.5
Reset
As with any automated device, it is important to assert RST# when the system is reset. When the
system comes out of reset, the system processor attempts to read from the flash memory if it is the
system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization
may occur because the flash memory may be providing status information rather than array data.
Flash memory devices from Intel allow proper CPU initialization following a system reset through
the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets
the system CPU.
After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status
Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output
drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a
process which takes a minimum amount of time to complete. When RST# has been deasserted, the
device is reset to asynchronous Read Array state.
Note:
If RST# is asserted during a program or erase operation, the operation is terminated and the
memory contents at the aborted location (for a program) or block (for an erase) are no longer valid,
because the data may have been only partially written or erased.
When returning from a reset (RST# deasserted), a minimum wait is required before the initial read
access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can
be initiated. After this wake
-
up interval passes, normal operation is restored. See
Section 7.0, “AC
Characteristics” on page 33
for details about signal-timing.
相关PDF资料 |
PDF描述 |
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| PF48F3P0ZTQ0 | Circular Connector; Body Material:Aluminum; Series:PT00; No. of Contacts:10; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Pin; Insert Arrangement:12-10 |
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| PF48F2P0ZT00 | Circular Connector; No. of Contacts:41; Series:; Body Material:Aluminum; Connector Shell Size:20; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:20-41 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PF48F2000P0ZBQ0 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F2000P0ZBQ0A | 功能描述:IC FLASH 64MBIT 85NS 88TPBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:StrataFlash™ 产品变化通告:Product Discontinuation 26/Apr/2010 标准包装:136 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步，DDR II 存储容量:18M（1M x 18） 速度:200MHz 接口:并联 电源电压:1.7 V ~ 1.9 V 工作温度:0°C ~ 70°C 封装/外壳:165-TBGA 供应商设备封装:165-CABGA（13x15） 包装:托盘 其它名称:71P71804S200BQ |
| PF48F2000P0ZTQ0 | 制造商:NUMONYX 制造商全称:Numonyx B.V 功能描述:Numonyx StrataFlash Embedded Memory |
| PF48F2000P0ZTQ0A | 功能描述:IC FLASH 64MBIT 85NS 88TPBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:StrataFlash™ 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 125°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) 其它名称:CAV24C32WE-GT3OSTR |
| PF48F2000W0YTQE | 制造商:Micron Technology Inc 功能描述:64X/0X QUAD 1.8 HF CUOSP - Tape and Reel |
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