PDC500 Input Specifications
PARAMETER
CONDITIONS/DESCRIPTION
MIN
NOM
MAX
UNITS
Input Voltage - DC
Continuous input range. Full power at 42-75 VDC.
36
75
VDC
Derate linearly from 40 VDC to 36 VDC, 400W.
Low Voltage Protection
Lowest DC input voltage.
34
VDC
Hold-up Time
At full load over DC input range.
17
ms
Input Current
48 VDC at full rated load.
14
ADC
Input Protection
Non-user serviceable internally located fuse.
Inrush Surge Current
Vin = 75 VDC, cold thermistor.
TBD
APK
Output Specifications (PFC500 and PDC500)
PARAMETER
CONDITIONS/DESCRIPTION
MIN
NOM
MAX
UNITS
Efficiency
Full rated load, 110 VAC (PFC500)/ 48VDC (PDC500).
75
%
Minimum loads
PFC/PDC500-1024
0.6
PFC500-1028
0.6
Amps
PFC500-1048
1.2
Ripple and Noise
Full load, 20 MHz bandwidth.
See Model Selection Charts
Output Power
300 LFM forced air cooling required for operation. See optional fan.
500
Watts
Continuous power, multiple output models. PDC500 requires derating below
42 VDC; see PDC500 input specifications.
Overshoot / Undershoot
Output voltage overshoot/undershoot at turn-on.
0
V
Regulation
Without connection of remote sense.
PFC/PDC500-1024
0.8
PFC500-1028
0.7
%
PFC500-1048
1.0
Transient Response
Recovery time, to within 1% of initial set point due to a 50-100% load change,
1ms
3% max. deviation.
Turn-on Delay
Time required for initial output voltage stabilization.
1
Sec
Turn-on Rise Time
Time required for output voltage to rise from 10% to 90%.
10
ms
Interface Signals and Internal Protection (PFC500 and PDC500)
PARAMETER
CONDITIONS/DESCRIPTION
MIN
NOM
MAX
UNITS
Overvoltage Protection
PFC/PDC500-1024
27.0
30.7
PFC500-1028
32.0
35.0
V
PFC500-1048
60.0
70.0
Overload Protection
Fully protected against output overload and short circuit. Automatic recovery upon removal of overload condition.
Overtemperature Protection
System shutdown due to excessive internal temperature, automatic reset.
Remote Sense
Total voltage compensation for cable losses with respect to the main output.
250
mV
Current Share
Accuracy of shared current with up to 6 parallel units.
10
%
Inhibit
TTL compatible logic signal will inhibit outputs by the application of a logic low signal.
An open circuit or external TTL high signal allows normal operation.
Input Power
TTL compatible logic signal. Time before regulation dropout due to
4ms
Fail Warning
loss of input power at 110 VAC.
Power Good
TTL compatible signal. Signal is low if main output is greater
PFC/PDC500-1024
22.08
27.36
or less than 10% of nominal. For models without the
PFC500-1028
25.20
30.80
V
“D” option, internal pull-up resistor is 1k
For “D” option,
PFC500-1048
44.20
54.72
pull-up resistor is 475 . See Apps Note #P1 for details.
Fan Voltage
Provides 170mA current to user supplied fan if fan option is not selected.
12
V
PFC500/PDC500 Series Data Sheet
AUG 01, 2003 revised to JUL 13, 2006
Page 2 of 4
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