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参数资料
| 型号： | PG2000P |
| 厂商： | Cardinal Components Inc. |
| 文件页数： | 3/5页 |
| 文件大小： | 0K |
| 描述： | OSC PROGRAMMER HAND HELD |
| 标准包装： | 1 |
| 类型： | 现场振荡器 |
| 适用于相关产品： | FIPO 零件 |
| 所含物品： | 编程器 |
| 相关产品： | SC-5320-ND - FIXTURE FOR 5 X 3.2MM SMD OSC SC2500-ND - PROG SOCKET CPPX8 SMT PLSTC PKG SC2000-ND - PROG SOCKET SMD CPPX7 5X7 PKG |
CARDINAL COMPONENTS
Field Programmable Blank Oscillator
? Programmed with the PG-3000, PG-3100 field oscillator programming
instrument within seconds
? Can be programmed twice
? Standard Package Options
Output Clock Switching Characteristics
Series CPP
Description
T EST C ONDITIONS
Min
Typ
Max Unit
Duty Cycle:
TTL @ 1.4 V
4.5-5.5 Vdd
Duty Cycle:
CMOS @ Vdd/2
4.5-5.5 Vdd
3.0–3.6 Vdd
< 50 MHz, C L = 50 pF
50–66 MHz, C L = 15 pF
66–125 MHz, C L = 25 pF
125–133 MHz, C L = 15 pF
< 66 MHz, C L < 25 pF
66–125 MHz, C L < 25 pF
125–133 MHz, C L < 15 pF
< 40 MHz, C L < 30 pF
40-100 MHz, C L < 15 pF
45
45
40
40
45
40
40
45
40
55
55
60
60
55
60
60
55
60
%
%
%
%
%
%
%
%
%
Output Clock Rise/Fall
0.8V–2.0V , 4.5-5.5 Vdd, C L = 50
0.8V–2.0V , 4.5-5.5 Vdd, C L = 25
0.8V–2.0V , 4.5-5.5 Vdd, C L = 15
0.2–0.8Vdd , 4.5-5.5 Vdd, C L = 50
0.2–0.8Vdd , 3.0–3.6 Vdd, C L = 30
0.2–0.8Vdd , 3.0–3.6 Vdd, C L = 15
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
Start Up Time
From power on
2
ms
Power Down Delay Time
Synchronous
Asynchronous
PWR_DWN pin LOW to output Hi-Z
T/2
10
T+10
15
ns
ns
Output Disable Time
Synchronous
Asynchronous
OE pin LOW to output Hi-Z
T = Frequency oscillator period
T/2
10
T+10
15
ns
ns
Output Enable Time
T
1.5 T + 25 ns
< 33.000 MHz
40
50
ps
RMS Period Jitter:
Peak to Peak *
> 33.000, MHz
< 33.000 MHz
> 33.000 MHz
30
100
75
40
250
175
ps
ps
ps
* Jitter tested at > 1,000,000 samples, exceeding JEDEC std JESD65.
Cardinal Components, Inc.
145 Route 46 West
Wayne, NJ 07470
Rev: E -0121511- 3
O-36
TEL: (973)785-1333
E-MAIL: sales@cardinalxtal.com
WEB: http://www.cardinalxtal.com
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