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| 型号： | PGA113AIDGSRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO10 |
| 封装： | GREEN, PLASTIC, MSOP-10 |
| 文件页数： | 13/47页 |
| 文件大小： | 1545K |
| 代理商： | PGA113AIDGSRG4 |
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SERIAL INTERFACE INFORMATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
DIN
DOUT
SPIMode0,0(CPOL=0,CPHA=0)
CS
SCLK
DIN
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SPIMode1,1(CPOL=1,CPHA=1)
SERIAL DIGITAL INTERFACE: SPI MODES
10 A
m
PGA116
PGA117
DOUT
DIN
SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com
Figure 58. SPI Mode 0,0 and Mode 1,1
Table 2. SPI Mode Setting Description
MODE
CPOL
CPHA
CPOL DESCRIPTION
CPHA DESCRIPTION
0, 0
0
0(1)
Clock idles low
Data are read on the rising edge of clock. Data change on the falling edge of clock.
1, 1
1
1(2)
Clock idles high
Data are read on the rising edge of clock. Data change on the falling edge of clock.
(1)
CPHA = 0 means sample on first clock edge (rising or falling) after a valid CS.
(2)
CPHA = 1 means sample on second clock edge (rising or falling) after a valid CS.
The PGA uses a standard serial peripheral interface
(SPI). Both SPI Mode 0,0 and Mode 1,1 are
supported, as shown in Figure 58 and described in
If there are not even-numbered increments of 16
clocks (that is, 16, 32, 64, and so forth) between CS
going low (falling edge) and CS going high (rising
edge), the device takes no action. This condition
provides reliable serial communication. Furthermore,
this condition also provides a way to quickly reset the
SPI interface to a known starting condition for data
synchronization.
Transmitted
data
are
latched
Figure 59. Digital I/O Structure—PGA116/PGA117
internally on the rising edge of CS.
On the PGA116/PGA117, CS, DIN, and SCLK are
Schmitt-triggered CMOS logic inputs. DIN has a weak
internal
pull-down
to
support
daisy-chain
communications on the PGA116/PGA117. DOUT is a
CMOS logic output. When CS is high, the state of
DOUT is high-impedance. When CS is low, DOUT is
driven as illustrated in Figure 59.
20
Copyright 2008, Texas Instruments Incorporated
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