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参数资料
| 型号： | PGA309AIPWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封装： | GREEN, PLASTIC, TSSOP-16 |
| 文件页数： | 19/24页 |
| 文件大小： | 661K |
| 代理商： | PGA309AIPWRG4 |
SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, VSA= VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF
= REFIN/REFOUT = +5V, unless otherwise noted.
PGA309
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Output Fine Gain Adjust (Gain DAC)
Range
0.33 to 1
V/V
Resolution
65,536 steps, 16-bit DAC
10
mV/V
Integral Nonlinearity
20
LSB
Differential Nonlinearity
0.5
LSB
Output Amplifier
Offset Voltage (RTI of Output Amplifier)
(4)
3
mV
vs Temperature
5
mV/°C
vs Supply Voltage, VSA
30
mV/V
Common-Mode Input Range
0
VS – 1.5
V
Input Bias Current
100
pA
Amplifier Internal Gain
Gain Range Steps
2, 2.4, 3, 3.6, 4.5, 6, 9
2 to 9
V/V
Initial Gain Error
2, 2.4, 3.6
0.25
±1
%
4.5
0.3
±1.2
%
6
0.4
±1.5
%
9
0.6
±2.0
%
vs Temperature
2, 2.4, 3.6
5
ppm/°C
4.5
5
ppm/°C
6
15
ppm/°C
9
30
ppm/°C
Output Voltage Range
(5)
RL = 10kΩ
0.1
4.9
V
Open-Loop Gain
115
dB
Gain-Bandwidth Product
2
MHz
Phase Margin
Gain = 2, CL = 200pF
45
deg
Output Resistance
AC Small-signal, open-loop, f = 1MHz, IO = 0
675
Over- and Under-Scale Limits
VREF = 4.096
Over-Scale Thresholds
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘000’
0.9708
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘001’
0.9610
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘010’
0.9394
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘011’
0.9160
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘100’
0.9102
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘101’
0.7324
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘110’
0.5528
Over-Scale Comparator Offset
+6
+60
+114
mV
Over-Scale Comparator Offset Drift
+0.37
mV/°C
Under-Scale Thresholds
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘111’
0.0605
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘110’
0.0547
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘101’
0.0507
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘100’
0.0449
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘011’
0.0391
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘010
0.0352
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘001’
0.0293
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘000’
0.0254
Unde-rScale Comparator Offset
7
50
+93
mV
Under-Scale Comparator Offset Drift
0.15
mV/°C
(4)
RTI = Referred-to-input. RTO = referred to output.
(5)
Unless limited by the over/under-scale setting.
4
Copyright 2003–2011, Texas Instruments Incorporated
Product Folder Link(s): PGA309
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