参数资料
| 型号： | PI2121-00-LGIZ |
| 厂商： | Vicor Corporation |
| 文件页数： | 7/21页 |
| 文件大小： | 0K |
| 描述： | IC OR CTRLR N-CH 17LGA |
| 产品培训模块： | Cool-ORing? Series |
| 标准包装： | 50 |
| 系列： | Picor®, Cool-ORing® |
| 应用： | 冗余电源，电信基础结构 |
| FET 型： | N 沟道 |
| 输出数： | 1 |
| 内部开关： | 是 |
| 电源电压： | 4.5 V ~ 13.2 V |
| 电流 - 电源： | 3.7mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | 管件 |
| 其它名称： | 1102-1107-5 |
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Forward Voltage Comparator: FWD
The FWD comparator detects when a forward
current condition exists and SP is 6mV positive with
respect to SN. When SP-SN is less than 6mV, the
FWD comparator will assert the Fault flag to report a
fault condition indicative of a light load “load not
present” condition or possible shorted MOSFET.
Forward Over Current Comparator: FOC
The FOC comparator indicates an excessive forward
current condition when SP is 66mV (typical) higher
than SN. When the FET is in the on-state and SP-
SN is higher than 66mV (typical) the PI2121 will
initiate a fault condition via the FT pin.
Slave:
In high current applications that exceed the single
PI2121 current handling capability, multiple PI2121’s
can be paralleled and synchronized by using the
slave function.
The Slave function synchronizes multiple PI2121’s
together and allows for localized control of each
paralleled MOSFET. One PI2121 will be designated
as the master and it will control the response of the
slaved PI2121’s.
When the PI2121 is configured in the “Master
Mode” by connecting the BK to ground, the SL will
be an output having the same signal characteristics
as the internal Gate Driver. In this configuration, the
SL output is capable of driving up to ten PI2121’s,
configured in “Slave Mode”, through their
corresponding SL pins. Logic high for the SL pin is
limited to 5.5V (max).
When the BK pin is tied to VC, the PI2121 becomes
UV:
The Under-Voltage (UV) input trip point can be
programmed through an external resistor divider to
monitor the input voltage. The UV comparator
initiates a fault condition and pulls the FT pin low,
when UV falls below the Under-Voltage Falling
Threshold. If the PI2121 is configured in a floating
application, where the GND pin is connected to the
input voltage, the UV pin cannot detect the input
voltage. In this case, the UV pin should be disabled
by connecting it to the VC pin.
OV:
The Over-Voltage (OV) input trip point can be
programmed through an external resistor divider to
monitor the input voltage. The OV comparator
initiates a fault condition and pulls the FT pin low
when OV rises above the Over-Voltage Rising
Threshold. If the PI2121 is configured in a floating
application, where the GND pin is connected to the
input voltage, the OV pin cannot detect the input
voltage. In this case, the OV pin should be disabled
by connecting it to the controller GND pin.
Over-Temperature Detection:
The internal Over-Temperature block monitors the
junction temperature of the controller. The over-
temperature threshold is set to 160 ° C with -10 ° C of
hysteresis. When the controller temperature
exceeds this threshold, the over-temperature circuit
initiates a fault condition and pulls the FT pin low.
Fault:
The fault circuit output is an open collector with 40 μ s
delay to prevent any false triggering. The FT pin
will be pulled low when any of the following faults
occur:
a slave and the SL pin will be an input. The
internal Gate driver section and reverse current
section are the only active circuits in the slaved
PI2121 while the master performs the diagnostics
and gate drive control.
VC and Internal Voltage Regulator:
The PI2121 has a separate input (VC) that provides
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Reverse Current
Forward Over-Current
Forward Low Current
Over-Temperature
Input Under-Voltage
Input Over-Voltage
VC pin Under-Voltage
power to the control circuitry and the internal gate
driver. An internal regulator clamps the VC voltage
to 15.5V.
For high side applications, the VC input should be
5V above the bus voltage to properly enhance the
internal N-channel MOSFET.
The internal regulator circuit has a comparator to
monitor the VC voltage and initiates a FAULT
condition when VC is lower than the VC Under-
Voltage Threshold
A gate voltage detector prevents FOC or FWD from
initiating a fault when the MOSFET is in an OFF
condition.
The only fault condition that initiates gate turn-off of
the MOSFET (as well as a fault flag signal) is when
the reverse current fault conditions are met. All other
f aul t conditions issue only a fault flag signal via the
FT p in, but do not affect the gate of the MOSFET.
The FT pin serves as an indicator that a fault
condition may be present. This information can be
reported to a Host to signal that some system level
maintenance may be required.
Picor Corporation ? picorpower.com
PI2121
Rev. 1.1
Page 7 of 21
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