参数资料
| 型号： | PI2EQX4432DZDEX |
| 厂商： | Pericom |
| 文件页数： | 2/6页 |
| 文件大小： | 0K |
| 描述： | IC PCI-E REPEATER/EQUALR 48TQFN |
| 标准包装： | 3,000 |
| 系列： | * |
2
PS8888A
04/26/07
PI2EQX4432D
2.5Gbps x2 Lane PCI Express Repeater / Equalizer
with Signal Detect and Flow-through Pinout
Pin Description
Pin #
Pin Name
I/O
Description
1
AI+
I
Positive CML Input Channel A with internal 50 Ohm pull down during normal opera-
tion (EN_A = 1). When EN_A = 0, this pin is a high-impedance.
2
AI-
I
Negative CML Input Channel A with internal 50 Ohm pull down during normal op-
eration (EN_A = 1). When EN_A =0, this pin is a high-impedance.
36
AO+
O
Positive CML Output Channel A internal 50 Ohm pull up during normal operation and
2KΩ pull up otherwise.
35
AO-
O
Negative CML Output Channel A with internal 50 Ohm pull up during normal opera-
tion and 2K-ohm pull up otherwise.
33
BI+
Posite CML Input Channel B with internal 50 Ohm pull down during normal opera-
tion (EN_B = 1). When EN_B = 0, this pin is a high-impedance.
32
BI-
I
Negative CML Input Channel B with internal 50 Ohm pull down during normal opera-
tion (EN_B = 1). When EN_B = 0, this pin is a high-impedance.
4
BO+
O
Positive CML Output Channel B with internal 50 Ohm pull up during normal opera-
tion and 2k–Ohm pull up otherwise.
5
BO-
O
Negative CMLOutput Channel B with internal 50 Ohm pull up during normal opera-
tion and 2k–Ohm pull up otherwise.
7
CI+
I
Positive CML Input Channel C with internal 50 Ohm pull down during normal opera-
tion (EN_C = 1). When EN_C = 0, this pin is a high-impedance.
8
CI-
I
Negative CML Input Channel C with internal 50 Ohm pull down during normal opera-
tion (EN_C = 1). When EN_C = 0, this pin is a high-impedance.
30
CO+
O
Positive CMLOutput Channel C with internal 50 Ohm pull up during normal opera-
tion and 2K-ohm pull up otherwise.
29
CO-
O
Negative CMLOutput Channel C with internal 50 Ohm pull up during normal opera-
tion and 2k–Ohm pull up otherwise.
27
DI+
I
Positive CML Input Channel D with internal 50 Ohm pull down during normal opera-
tion (EN_D = 1). When EN_D = 0, this pin is a high-impedance.
26
DI-
I
Negative CML Input Channel D with internal 50 Ohm pull down during normal op-
eration (EN_D = 1). When EN_D = 0, this pin is a high-impedance.
10
DO+
O
Positive CML Output Channel D with internal 50 Ohm pull up during normal opera-
tion and 2k–Ohm pull up otherwise.
11
DO-
O
Negative CML Output Channel D with internal 50
Ω pull up during normal operation
and 2k–Ohm pull up otherwise.
41, 40, 39, 38
EN_[A, B,
C, D]
I
EN_[A:D] is a channel enable pin with internal 50k–Ohm pull-up resistor. ALVCMOS
high provides normal operation. ALVCMOS low selects a low power down mode.
43, 42, 20, 21
SEL–DE_
[A:D]
I
Output De–Emphasis conguration input for channels A, B, C and D, with internal
50k–Ohm pull up.Refer to table for modes.
47, 46, 16, 17
SEL–EQ_
[A:D]
I
Equalizer conguration input for channels A, B, C and D, with internal 50k–Ohm
pull-up. Refer to table for modes.
45, 44, 18, 19
SEL–OL_
[A:D]
I
Output Level conguration input for channels A, B, C, and D, with internal 50k–Ohm
pull–up. Refer to table for modes.
14, 15
CLK+,
CLK–
I
Differential input reference clock, typically 100MHz
22, 23
CLKO,
CLKO–
O
Differential reference clock output
13
EN_CLK
I
Enable Clock input with 50K–Ohm pull-up. When EN_CLK is LVCMOS high level,
the clock output operates normally. When EN_CLK = low, the clock outputs are
turned off for power savings. A clock is not required bt the data channels for opera-
tion.
07-0106
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