参数资料
型号: PI6C184S
英文描述: THIRTEEN DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|SOP|28PIN|PLASTIC
中文描述: 13个分布式输出时钟驱动器|的CMOS |专科| 28脚|塑料
文件页数: 3/12页
文件大小: 580K
代理商: PI6C184S
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P8399-1 06/11/99
PI6C102-16
Spread Spectrum Clock Synthesizer
CPUCLK
(Internal)
CPUCLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
(External)
Power Management Timing
Notes:
1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs
between when the clock disable goes low/high to when the first valid clock comes out of
the device.
2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid
clocks are driven from the device.
CPU_STOP# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F.
4. ON/OFF latency shown in the diagram is 2 CPU clocks.
5. All other clocks continue to run undisturbed.
6. PWR_DWN# and PCI_STOP# are shown in a HIGH state.
7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
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