参数资料
型号: PI6C21200AE
厂商: Pericom
文件页数: 7/14页
文件大小: 0K
描述: IC 1:12 CLOCK DVR PCI-EX 56TSSOP
产品培训模块: Total Timing Technology
标准包装: 35
系列: PCI Express® (PCIe)
类型: 时钟缓冲器/驱动器,多路复用器
PLL:
主要目的: PCI Express(PCIe)
输入: HCSL
输出: HCSL
电路数: 1
比率 - 输入:输出: 1:12
差分 - 输入:输出: 是/是
频率 - 最大: 400MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 56-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 56-TSSOP
包装: 管件
2
PS8821B
10/14/09
PI6C21200
1:12 Clock Driver for Intel
PCI Express Chipsets
Pin Descriptions
Pin Name
Type
Pin Number
Descriptions
PLL_BW#
Input
1
3.3V LVTTL input for selecting the PLL bandwidth. (High = Low BW)
SRC & SRC#
Input
2, 3
0.7V Differential SRC input from PI6C410B clock synthesizer
OUT[0:9] &
OUT[0:9]#
Output
6, 7, 9, 10, 13, 14, 16, 17,
19, 20, 24, 25, 32, 33,
35, 36, 39, 40, 42, 43
0.7V Differential outputs, geared to the ratio of input clock. Can be
congured to be 1:1 ratio.
OUT[10:11] &
OUT[10:11]#
Output
47, 48, 51, 52
0.7V Differential outputs, geared to the ratio of input clock same as
OUT[0:9]. Can be congured to be 1:1 ratio.
OE_[0:9]#
Input
5, 8, 15, 18, 21, 26, 31,
34, 41, 44
3.3V LVTTL input for enabling outputs, active low. Control each
OUT[0:9] pair.
OE_10#_11#
Input
53
3.3V LVTTL input for enabling outputs, active low. Control each
OUT[10:11] pair.
SA_[0:1]
Input
4, 27
3.3V LVTTL input for selecting the SMBus address
SA_2 / PLL-
BYPASS#
Input
30
3.3V LVTTL input for selecting fan-out of PLL operation, and SMBus
address. 0 = PLL Bypass, 1 = PLL mode
SCLK
Input
29
SMBus compatible SCLOCK input
SDA
I/O
28
SMBus compatible SDATA
IREF
Input
54
External resistor connection to set the differential output current
FS_A
Input
46
3.3V LVTTL inputs for CPU frequency selection
0 = above 200 MHz, 1 = below 200 MHz
VTT_PWRGD#
/ PWRDWN
Input
45
3.3V LVTTL input for Power Down operation, active high
VDD
Power
11, 22, 38, 50
3.3V Power Supply for Outputs
VSS
Ground
12, 23, 37, 49
Ground for Outputs
VSS_A
Ground
55
Ground for PLL
VDD_A
Power
56
3.3V Power Supply for PLL
Serial Data Interface (SMBus)
PI6C21200 is a slave only SMBus device that supports random byte read and write indexed block read and write protocol using a
single 7-bit address and read/write bit as shown below.
SMBus Address Selection by SA_[0:2]
SA_2/
PLLBypass#
SA_1
SA_0
SMBus
Address
PLL
Mode
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D0
D2
D4
D6
D8
DA
DC
DE
Bypass
PLL
09-0003
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