参数资料
型号: PI6C2308-3WI
厂商: Pericom Semiconductor Corp.
英文描述: 3.3V Zero-Delay Buffer
中文描述: 3.3零延时缓冲器
文件页数: 1/10页
文件大小: 506K
代理商: PI6C2308-3WI
1
PS8384D 06/26/01
Product Features
10 MHz to 134 MHz operating range
Zero input-output propagation delay, adjustable by external
capacitive load on FBK input
Multiple configurations, see Available PI6C2308
Configurations table
Input to output delay, less than 200ps
Multiple low skew outputs
- Output-output skew less than 200ps
- Device-device skew less than 600ps
- Two banks of four outputs, Hi-Z by two select inputs
Low Jitter, less than 200ps
3.3V operation
Space-saving Packages:
16-pin, 150-mil SOIC package (W16) (-1, -1H, -2, -3, -4, -6)
16-pin TSSOP package (L16) (-1, -1H)
Available in industrial and commercial temperatures
Functional Description
Providing two banks of four outputs, the PI6C2308 is a 3.3V zero-
delay buffer designed to distribute clock signals in applications
including PC, workstation, datacom, telecom, and high-performance
systems. Each bank of four outputs can be controlled by the select
inputs as shown in the Select Input Decoding Table.
The PI6C2308 provides 8 copies of a clock signal that has 200ps
phase error compared to a reference clock. The skew between the
output clock signals for PI6C2308 is less than 200ps. When there
are no rising edges on the REF input, the PI6C2308 enters a power
down state. In this mode, the PLL is off and all outputs are Hi-Z.
This results in less than 12μA of current draw. The Select Input
Decoding Table shows additional examples when the PLL shuts
down. The PI6C2308 configuration table shows all available devices.
The base part, PI6C2308-1, provides output clocks in sync with a
reference clock. With faster rise and fall times, the PI6C2308-1H
is the high drive version of the PI6C2308-1. Depending on which
output drives the feedback pin, PI6C2308-2 provides 2X and 1X
clock signals on each output bank. The PI6C2308-3 allows the user
to obtain 4X and 2X frequencies on the outputs. The PI6C2308-4
provides 2X clock signals on all outputs. PI6C2308 (-1, -2, -3, -4) allows
bank B to be Hi-Z when all output clocks are not required.The
PI6C2308-6 allows bank B to switch from Reference clock to half
of the frequency of Reference clock using the control inputs S1 and
S2 if Bank A is connected to feedback FBK. In addition, using the
control inputs S1 and S2, the PI6C2308-6 allows bank A to switch
from Reference clock to 2X the frequency of Reference clock if
Bank B is connected to feedback FBK. For testing purposes, the
select inputs connect the input clock directly to outputs.
Block Diagrams
Pin Configuration PI6C2308 (1, 1H, 2, 3, 4, 6)
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
1
2
3
V
DD
4
GND
5
CLKA2
6
CLKB2
7
S1
8
CLKB1
FBK
CLKA3
V
DD
CLKB4
CLKB3
S2
16
15
14
13
12
11
10
9
REF
CLKA1
GND
CLKA4
16-Pin
W, L
PLL
MUX
REF
S2
S1
Select Input
Decoding
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB2
CLKB3
CLKB4
CLKB1
PI6C2308-6
MUX
÷2
÷2
PLL
MUX
Extra Divider (-3, -4)
Extra Divider (-2,-3)
REF
S2
S1
Select Input
Decoding
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB2
CLKB3
CLKB4
CLKB1
PI6C2308 (-1, -1H, -2, -3, -4)
÷2
相关PDF资料
PDF描述
PI6C2308-4W 3.3V Zero-Delay Buffer
PI6C2308-4WI 3.3V Zero-Delay Buffer
PI6C2308-6W 3.3V Zero-Delay Buffer
PI6C2308-1HL 3.3V Zero-Delay Buffer
PI6C2308-1HLI 3.3V Zero-Delay Buffer
相关代理商/技术参数
参数描述
PI6C2308-4W 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer
PI6C2308-4WI 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer
PI6C2308-6W 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer
PI6C2308-6WI 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer
PI6C2308A 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer