参数资料
型号: PI6C2308A-2W
厂商: Pericom Semiconductor Corp.
英文描述: 3.3V Zero-Delay Buffer
中文描述: 3.3零延时缓冲器
文件页数: 1/10页
文件大小: 387K
代理商: PI6C2308A-2W
1
PS8385B 08/03/00
Product Features
10 MHz to 140 MHz operating range
Zero input-output propagation delay, adjustable by
capacitive load on FBK input
Multiple configurations, see Available PI6C2308A
Configurations table
Input to output delay, less than 150ps
Multiple low skew outputs
- Output-output skew less than 200ps
- Device-device skew less than 500ps
- Two banks of four outputs, Hi-Z by two select inputs
Low Jitter, less than 200ps
3.3V operation
Available in industrial &commercial temperatures
Packages:
- Space-saving 16-pin, 150-mil SOIC (W)
- 16-pin TSSOP (L)
Functional Description
Providing two banks of four outputs, the PI6C2308A is a 3.3V zero-
delay buffer designed to distribute clock signals in applications
including PC, workstation, datacom, telecom, and high-performance
systems. Each bank of four outputs can be controlled by the select
inputs as shown in the Select Input Decoding Table.
The PI6C2308A provides 8 copies of a clock signal that has 150ps
phase error compared to a reference clock. The skew between the
output clock signals for PI6C2308A is less than 200ps. When there
are no rising edges on the REF input, the PI6C2308A enters a power
down state. In this mode, the PLL is off and all outputs are Hi-Z. This
results in less than 12
μ
A of current draw. The Select Input Decoding
table shows additional examples when the PLL shuts down. The
PI6C2308A configuration table shows all available devices.
The base part, PI6C2308A-1, provides output clocks in sync with
a reference clock. With faster rise and fall times, the PI6C2308A-1H
is the high-drive version of the PI6C2308A-1. Depending on which
output drives the feedback pin, PI6C2308A-2 provides 2X and 1X
clock signals on each output bank. The PI6C2308A-3 allows the user
to obtain 4X and 2X frequencies on the outputs. The PI6C2308A-4
provides 2X clock signals on all outputs. PI6C2308A (-1, -2, -3, -4)
allows bank B to be Hi-Z when all output clocks are not required.The
PI6C2308A-6 allows bank B to switch from Reference clock to half
of the frequency of Reference clock using the control inputs S1 and
S2 if Bank A is connected to feedback FBK. In addition, using the
control inputs S1 and S2, the PI6C2308A-6 allows bank A to switch
from Reference clock to 2X the frequency of Reference clock if Bank
B is connected to feedback FBK. For testing purposes, the select
inputs connect the input clock directly to outputs.
Block Diagrams
Pin Configuration PI6C2308A (-1, -1H, -2, -3, -4, -6)
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3.3V Zero-Delay Buffer
PI6C2308A
1
2
3
VDD
GND
4
5
CLKA2
6
CLKB2
7
S1
8
CLKB1
FBK
CLKA3
VDD
GND
CLKB4
CLKB3
S2
16
15
14
13
12
11
10
9
REF
CLKA1
CLKA4
16-Pin
W, L
PLL
MUX
REF
S2
S1
Select Input
Decoding
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB2
CLKB3
CLKB4
CLKB1
PI6C2308A-6
MUX
÷2
÷2
PLL
MUX
Extra Divider (-3, -4)
Extra Divider (-2,-3)
REF
S2
S1
Select Input
Decoding
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB2
CLKB3
CLKB4
CLKB1
PI6C2308A (-1, -1H, -2, -3, -4)
÷2
相关PDF资料
PDF描述
PI6C2308A-2WI 3.3V Zero-Delay Buffer
PI6C2308A-3 3.3V Zero-Delay Buffer
PI6C2308A-3W 3.3V Zero-Delay Buffer
PI6C2308A-4 3.3V Zero-Delay Buffer
PI6C2308A-4W 3.3V Zero-Delay Buffer
相关代理商/技术参数
参数描述
PI6C2308A-2WI 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer
PI6C2308A-3 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer
PI6C2308A3L 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer
PI6C2308A-3L 制造商:未知厂家 制造商全称:未知厂家 功能描述:Eight Distributed-Output Clock Driver
PI6C2308A-3LI 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer