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| 型号： | PI6C3991-IJ |
| 厂商： | Pericom Semiconductor Corp. |
| 英文描述： | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| 中文描述： | 3.3V的高速，低电压偏差可编程时钟缓冲器SuperClock |
| 文件页数： | 8/11页 |
| 文件大小： | 500K |
| 代理商： | PI6C3991-IJ |
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PS8450B 04/09/01
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Figure 3 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between outputs,
the SuperClock can be programmed to stagger the timing of its
outputs. The four groups of output pairs can each be programmed
to different output timing. Skew timing can be adjusted over a wide
range in small increments with the appropriate strapping of the
function select pins. In this configuration the 4Q0 output is fed back
to FB and configured for zero skew.
The other three pairs of outputs are programmed to yield different
skews relative to the feedback. By advancing the clock signal on the
longer traces or retarding the clock signal on shorter traces, all loads
can receive the clock pulse at the same time.
In this illustration the FB input is connected to an output with 0ns
skew (xF1, xF0 = MID) selected. The internal PLL synchronizes the
FB and REF inputs and aligns their rising edges to insure that all
outputs have precise phase alignment.
Clock skews can be advanced by ±6 time units (t
U
) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed. Since
Zero Skew, +t
U
, and t
U
are defined relative to output groups, and
since the PLL aligns the rising edges of REF and FB, it is possible to
create wider output skews by proper selection of the xFn inputs. For
example a +10 t
U
between REF and 3Qx can be achieved by connect-
ing 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 =
High. (Since FB aligns at 4 t
U
and 3Qx skews to +6 t
U
, a total of +10
t
U
skew is realized). Many other configurations can be realized by
skewing both the output used as the FB input and skewing the other
outputs.
Figure 4. Inverted Output Connections
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
Figure 4 shows an example of the invert function of the SuperClock.
In this example the 4Q0 output used as the FB input is programmed
for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs
are programmed for zero skew. When 4F0 and 4F1 are tied HIGH, 4Q0
and 4Q1 become inverted zero phase outputs. The PLL aligns the
rising edge of the FB input with the rising edge of the REF. This
causes the 1Q, 2Q, and 3Q outputs to become the inverted outputs
with respect to the REF input. By selecting which output is connect
to FB, it is possible to have 2 inverted and 6 non-inverted outputs
or 6 inverted and 2 non-inverted outputs. The correct configura-tion
would be determined by the need for more (or fewer) inverted
outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate
for varying trace delays independent of inver-sion on 4Q.
Figure 5. Frequency Multiplier with Skew Connections
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
20 MHz
40 MHz
20 MHz
80 MHz
Figure 5 illustrates the SuperClock configured as a clock multiplier.
The 3Q0 output is programmed to divide by four and is fed back to
FB. This causes the PLL to increase its frequency until the 3Q0 and
3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx outputs run
at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by
two, which results in a 40 MHz waveform at these outputs. Note that
the 20 and 40 MHz clocks fall simultaneously and are out of phase
on their rising edge. This will allow the designer to use the rising
edges of the frequency and frequency outputs without concern
for rising-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80
MHz and are skewed by programming their select inputs accord-
ingly. Note that the FS pin is wired for 80 MHz operation because that
is the frequency of the fastest output.
相关PDF资料 |
PDF描述 |
|---|---|
| PI6C3991-5IJ | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3991-5J | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3991 | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3991J | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3Q991-2J | 3.3V Programmable Skew PLL Clock Driver |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PI6C3991J | 功能描述:IC PROG SKEW CLOCK DRIVER 32PLCC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:SuperClock® 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| PI6C3991JE | 功能描述:锁相环 - PLL Programmable Skew Zero Delay RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| PI6C3991JI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Eight Distributed-Output Clock Driver |
| PI6C3Q991 | 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V Programmable Skew PLL Clock Driver |
| PI6C3Q991-2 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Eight Distributed-Output Clock Driver |
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