参数资料
型号: PI6C3991
厂商: Pericom Semiconductor Corp.
英文描述: 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock
中文描述: 3.3V的高速,低电压偏差可编程时钟缓冲器SuperClock
文件页数: 9/11页
文件大小: 500K
代理商: PI6C3991
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PI6C3991
3.3V High-Speed, Low-Voltage Programmable
9
PS8450B 04/09/01
Figure 6. Frequency Divider Connections
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
20 MHz
10 MHz
5 MHz
20 MHz
Figure 6 demonstrates the SuperClock in a clock divider application.
2Q0 is fed back to the FB input and programmed for zero skew. 3Qx
is programmed to divide by four. 4Qx is programmed to divide by two.
Note that the falling edges of the 4Qx and 3Qx outputs are aligned.
This allows use of the rising edges of the frequency and
frequency without concern for skew mismatch. The 1Qx outputs are
programmed to zero skew and are aligned with the 2Qx outputs. In
this example, the FS input is grounded to configure the device in the
15 to 30 MHz range since the highest frequency output is running
at 20 MHz.
Figure 7 shows some of the functions that are selectable on the 3Qx
and 4Qx outputs. These include inverted outputs and outputs that
offer divide-by-2 and divide-by-4 timing. An inverted output allows
the system designer to clock different sub-systems on opposite
edges, without suffering from the pulse asymmetry typical of non-
ideal loading. This function allows the two subsystems to each be
clocked 180 degrees out of phase, but still to be aligned within the
skew spec.
The divided outputs offer a zero-delay divider for portions of the
system that need the clock to be divided by either two or four, and
still remain within a narrow skew of the 1X clock. Without this
feature, an external divider would need to be add-ed, and the
propagation delay of the divider would add to the skew between the
different clock signals.
These divided outputs, coupled with the Phase Locked Loop, allow
the SuperClock to multiply the clock rate at the REF input by either
two or four. This mode will enable the designer to distribute a low-
frequency clock between various portions of the system, and then
locally multiply the clock rate to a more suitable frequency, while still
maintaining the low-skew characteristics of the clock driver. The
SuperClock can perform all of the functions described above at the
same time. It can multiply by two and four or divide by two (and four)
at the same time that it is shifting its outputs over a wide range or
maintaining zero skew between selected outputs.
Figure 7. Multi-Function Clock Driver
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
27.5 MHz
Distribution
Clock
REF
LOAD
LOAD
LOAD
LOAD
Z
0
Z
0
Z
0
Z
0
80 MHz
Inverted
27.5 MHz
80 MHz
Zero Skew
80 MHz Skewed
–3.125ns (–4t
U
)
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PI6C39911 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
PI6C399111J 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
PI6C39911-2 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:Clock IC | 250ps Accuracy. 3.3V. LVTTL. 3.75 to 110 MHz
PI6C39911-2J 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
PI6C39911-2JE 功能描述:锁相环 - PLL Programmable Skew Zero Delay RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray