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参数资料
| 型号： | PI6C3Q991-2J |
| 厂商： | Pericom Semiconductor Corp. |
| 英文描述： | 3.3V Programmable Skew PLL Clock Driver |
| 中文描述： | 3.3V的可编程偏移PLL时钟驱动器 |
| 文件页数： | 3/10页 |
| 文件大小： | 544K |
| 代理商： | PI6C3Q991-2J |
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PI6C3Q991, PI6C3Q993
3
PS8449A 10/09/00
Programmable Skew
Output skew with respect to the REF input is adjustable to compen-
sate for PCB trace delays, backplane propagation delays or to
accommodate requirements for special timing relationships between
clocked components. Skew is selectable as a multiple of a time unit
t
U
which is of the order of a nanosecond (see Table 2). There are 9
skew configurations available for each output pair. These configu-
rations are choosen by the nF1:0 control pins. In order to minimize
the number of control pins, 3-level inputs (HIGH-MID-LOW) are
used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew
is not a requirement, the control pins can be left open for the zero skew
default setting. The Skew Selection Table (Table 3) shows how to
select specific skew taps by using the nF1:0 control pins.
External Feedback
By providing external feedback, the PI6C3Q99X family gives users
flexibility with regard to skew adjustment. The FB signal is compared
with the input REF signal at the phase detector in order to drive the
VCO. Phase differences cause the VCO of the PLL to adjust upwards
or downwards accordingly. An internal loop filter moderates the
response of the VCO to the phase detector. The loop filter transfer
function has been chosen to provide minimal jitter (or frequency
variation) while still providing accurate responses to input fre-
quency changes.
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Table 2. PLL Programmable Skew Range and Resolution Table
Notes:
1. The device may be operated outside recommended frequency ranges without damage, but functional
operation is not guaranteed. Selecting the appropriate FS value based on input frequency range allows the
PLL to operate in its sweet spot where jitter is lowest.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator.
The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their
undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the
output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO
frequency when the part is configured for a frequency multiplication by using a divided output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used
for feedback, then adjustment range will be greater. For example if a 4t
U
skewed output is used for feedback,
all other outputs will be skewed 4t
U
in addition to whatever skew value is programmed for those outputs.
Max adjustment range applies to output pairs 3 and 4 where ±6 t
U
skew adjustment is possible and at the
lowest F
NOM
value.
相关PDF资料 |
PDF描述 |
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| PI6C39911A | No RSENSE Current Mode Synchronous Step-Down Switching Regulator; Package: SO; No of Pins: 16; Temperature Range: -40°C to +85°C |
| PI6C39911A-2 | Clock IC | 250ps Accuracy. 3.3V. LVTTL. 3.75 to 110 MHz |
| PI6C39911A-5 | Clock IC | 500ps Accuracy. 3.3V. LVTTL. 3.75 to 110 MHz |
| PI6C39911J | Monolithic Synchronous Step-Down Switching Regulator; Package: SO; No of Pins: 8; Temperature Range: -40°C to +85°C |
| PI6C3991-2 | Clock IC | 250ps Accuracy. 3.3V. LVTTL. 3.75 to 80 MHz |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PI6C3Q991-5 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Clock IC | 500ps Accuracy. 3.3V. Balanced. 3.75 to 85 MHz |
| PI6C3Q991-5I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Eight Distributed-Output Clock Driver |
| PI6C3Q991-5IJ | 制造商:Pericom Semiconductor Corporation 功能描述:Programmable PLL Clock Driver Single 32-Pin PLCC |
| PI6C3Q991-5J | 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3.3V Programmable Skew PLL Clock Driver |
| PI6C3Q991A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Clock IC | 750ps Accuracy. 3.3V. Balanced. 3.75 to 85 MHz |
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