参数资料
| 型号： | PI74ALVTC16373A |
| 厂商： | Pericom |
| 文件页数： | 1/10页 |
| 文件大小： | 0K |
| 描述： | IC 16-BIT TRANSP LATCH 48-TSSOP |
| 产品变化通告： | Product Discontinuation Notice 29/May/2007 |
| 标准包装： | 39 |
| 系列： | 74ALVTC |
| 逻辑类型： | D 型透明锁存器 |
| 电路： | 8:8 |
| 输出类型： | 三态 |
| 电源电压： | 1.8 V ~ 3.6 V |
| 独立电路： | 2 |
| 延迟时间 - 传输： | 1ns |
| 输出电流高，低： | 6mA，6mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 48-TSSOP |
| 包装： | 管件 |
1
PS8355D
07/22/08
Product Description
The PI74ALVTC16373 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as two 8-bit latches or one 16-bit
latch. When the Latch Enable (LE) input is HIGH, the Q outputs
follow the (D) inputs. When LE is taken LOW, the Q outputs are
latched at the levels set up at the D inputs.
A buffered Output Enable (OE) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or
a high-impedance state in which the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the
increased drive provide the capability to drive bus lines without an
interface or pullup components. OE does not affect internal
operations of the latch. Old data can be retained or new data can be
entered while the ouputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VDD through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.8/3.6V systems, and “Bus Hold,” which retains the data
input’s last state whenever the data input goes to high-impedance,
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Product Features
PI74ALVTC family is designed for low-voltage operation,
VDD=1.8Vto3.6V
Supports Live Insertion
3.6V I/O Tolerant Inputs and Outputs
Bus Hold
High Drive, –32/64mA @ 3.3V
Uses patented noise reduction circuitry
Power-off high-impedance inputs and outputs
Industrial operation at –40°C to +85°C
Packaging (Pb-free and Green available):
– 48-pin 240 mil wide plastic TSSOP (A)
PI74ALVTC16373
16-Bit Transparent D-Type Latch
with 3-State Outputs
Logic Block Diagram
1LE
1Q1
1D
C1
1D1
To Seven Other Channels
1OE
1
48
47
2
2LE
2Q1
1D
C1
2D1
To Seven Other Channels
25
36
13
24
2OE
08-0291
相关PDF资料 |
PDF描述 |
|---|---|
| PI74ALVTC16374AEX | IC 16BIT EDGE-TRIG D FF 48TSSOP |
| PI74AVC+16244AE | IC BUFF DVR TRI-ST 16BIT 48TSSOP |
| PI74AVC+16820AAE | IC FLIP FLOP 3ST 10BIT 56TSSOP |
| PI74AVC+16836A | IC UNIV BUS DVR 20BIT 56TSSOP |
| PI74AVC16834AEX | IC UNIV BUS DVR 18BIT 56TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PI74ALVTC16373AE | 功能描述:闭锁 16B Edge Trigered D type RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| PI74ALVTC16373AEX | 功能描述:闭锁 16B Edge Trigered D type RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| PI74ALVTC16373K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit D-Type Latch |
| PI74ALVTC16373KE | 功能描述:闭锁 16B Edge Trigered D type RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| PI74ALVTC16373KEX | 功能描述:闭锁 16B Edge Trigered D type RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。