参数资料
| 型号： | PI7C8154BNAIE |
| 厂商： | Pericom |
| 文件页数： | 3/114页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 产品变化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 标准包装： | 27 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 304-BBGA |
| 供应商设备封装： | 304-PBGA（31x31） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 100 of 114
JUNE 2008 REVISION 1.1
15
BRIDGE BEHAVIOR
A PCI cycle is initiated by asserting the FRAME# signal. In a bridge, there are a number of
possibilities. Those possibilities are summarized in the table below:
15.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES
Initiator
Target
Response
Master on Primary
Target on Primary
PI7C8154B does not respond. It detects this
situation by decoding the address as well as
monitoring the P_DEVSEL# for other fast and
medium devices on the Primary Port.
Master on Primary
Target on Secondary
PI7C8154B asserts P_DEVSEL#, terminates
the cycle normally if it is able to be posted,
otherwise return with a retry. It then passes the
cycle to the appropriate port. When the cycle is
complete on the target port, it will wait for the
initiator to repeat the same cycle and end with
normal termination.
Master on Primary
Target not on Primary nor
Secondary Port
PI7C8154B does not respond and the cycle will
terminate as master abort.
Master on Secondary
Target on the same
Secondary Port
PI7C8154B does not respond.
Master on Secondary
Target on Primary or the
other Secondary Port
PI7C8154B asserts S_DEVSEL#, terminates
the cycle normally if it is able to be posted,
otherwise returns with a retry. It then passes
the cycle to the appropriate port. When cycle is
complete on the target port, it will wait for the
initiator to repeat the same cycle and end with
normal termination.
Master on Secondary
Target not on Primary nor
the other Secondary Port
PI7C8154B does not respond.
15.2
ABNORMAL TERMINATION (INITIATED BY BRIDGE
MASTER)
15.2.1
MASTER ABORT
Master abort indicates that when PI7C8154B acts as a master and receives no response (i.e., no
target asserts DEVSEL# or S_DEVSEL#) from a target, the bridge deasserts FRAME# and then
de-asserts IRDY#.
15.2.2
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, P_PAR64,
S_PAR, and S_PAR64 signals. Parity should be even (i. e. an even number of‘1’s) across AD,
CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are valid. For
reads, even parity must be generated using the initiators CBE signals combined with the read data.
Again, the PAR signal corresponds to read data from the previous data phase cycle.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8154EVB | 功能描述:界面开发工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
| PI7C81552 | 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C9X110 | 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:PCI Express-to-PCI Reversible Bridge |
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