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参数资料
型号： PI90LV031AWEX
厂商： Pericom
文件页数： 6/11页
文件大小： 0K
描述： IC LINE DVR QUAD LVDS 3V 16-SOIC
标准包装： 3,000
类型： 收发器
驱动器/接收器数： 4/0
规程： LVDS
电源电压： 3 V ~ 3.6 V
安装类型： 表面贴装
封装/外壳： 16-SOIC（0.154"，3.90mm 宽）
供应商设备封装： 16-SOIC
包装： 带卷 (TR)
4
DS657F3
CS4265
6.3.1 DAC Digital Interface Format (Bits 5:4) ................................................................................. 37
6.3.2 Mute DAC (Bit 2) ................................................................................................................... 37
6.3.3 De-Emphasis Control (Bit 1) .................................................................................................. 38
6.4 ADC Control - Address 04h ............................................................................................................ 38
6.4.1 Functional Mode (Bits 7:6) .................................................................................................... 38
6.4.2 ADC Digital Interface Format (Bit 4) ...................................................................................... 38
6.4.3 Mute ADC (Bit 2) ................................................................................................................... 39
6.4.4 ADC High-Pass Filter Freeze (Bit 1) ..................................................................................... 39
6.4.5 Master / Slave Mode (Bit 0) ................................................................................................... 39
6.5 MCLK Frequency - Address 05h .................................................................................................... 39
6.5.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 39
6.6 Signal Selection - Address 06h ...................................................................................................... 40
6.6.1 DAC SDIN Source (Bit 7) ...................................................................................................... 40
6.6.2 Digital Loopback (Bit 1) ......................................................................................................... 40
6.7 Channel B PGA Control - Address 07h .......................................................................................... 40
6.7.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 40
6.8 Channel A PGA Control - Address 08h .......................................................................................... 40
6.8.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 40
6.9 ADC Input Control - Address 09h ................................................................................................... 41
6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 41
6.9.2 Analog Input Selection (Bit 0) ................................................................................................ 41
6.10 DAC Channel A Volume Control - Address 0Ah ........................................................................... 41
6.11 DAC Channel B Volume Control - Address 0Bh ........................................................................... 42
6.11.1 Volume Control (Bits 7:0) .................................................................................................... 42
6.12 DAC Control 2 - Address 0Ch ...................................................................................................... 42
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6) ................................................................ 42
6.12.2 Invert DAC Output (Bit 5) .................................................................................................... 43
6.13 Status - Address 0Dh ................................................................................................................... 43
6.13.1 E to F C-Buffer Transfer ...................................................................................................... 43
6.13.2 Clock Error (Bit 3) ................................................................................................................ 43
6.13.3 ADC Overflow (Bit 1) ........................................................................................................... 43
6.13.4 ADC Underflow (Bit 0) ......................................................................................................... 43
6.14 Status Mask - Address 0Eh .......................................................................................................... 44
6.15 Status Mode MSB - Address 0Fh ................................................................................................. 44
6.16 Status Mode LSB - Address 10h .................................................................................................. 44
6.17 Transmitter Control 1 - Address 11h ............................................................................................ 44
6.17.1 E to F C-Data Buffer Transfer Inhibit (Bit 6) ........................................................................ 44
6.17.2 C-Data Access Mode (Bit 5) ................................................................................................ 44
6.18 Transmitter Control 2 - Address 12h ............................................................................................ 45
6.18.1 Transmitter Digital Interface Format (Bits 7:6) .................................................................... 45
6.18.2 Transmitter Output Driver Control (Bit 5) ............................................................................. 45
6.18.3 Transmitter Mute Control (Bit 4) .......................................................................................... 45
6.18.4 Transmitted Validity Bit Control (Bit 3) ................................................................................45
6.18.5 Transmitter Mono/Stereo Operation Control (Bit 2) ............................................................. 45
6.18.6 Mono Mode CS Data Source (Bit 1) .................................................................................... 45
6.18.7 Mono Mode Channel Selection (Bit 0) ................................................................................. 46
7. PARAMETER DEFINITIONS ................................................................................................................ 47
8. DAC FILTER PLOTS
.................................................................................................................... 48
9. ADC FILTER PLOTS
......................................................................................................................... 50
10. EXTERNAL IEC60958-3 TRANSMITTER COMPONENTS ............................................................... 52
10.1 IEC60958-3 Transmitter External Components ............................................................................ 52
10.2 Isolating Transformer Requirements ............................................................................................ 52
11. CHANNEL STATUS BUFFER MANAGEMENT ................................................................................ 53
11.1 IEC60958-3 Channel Status (C) Bit Management ........................................................................ 53
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PI90LV032A 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:3V LVDS High-Speed Differential Line Drivers
PI90LV032AL 制造商:Pericom Semiconductor Corporation 功能描述:LVDS Receiver 16-Pin TSSOP
PI90LV032ALE 功能描述:总线接收器 LVDS Receiver (EN) Quad RoHS:否 制造商:Texas Instruments 接收机数量:4 接收机信号类型:Differential 接口类型:EIA/TIA-422-B, V.11 工作电源电压:3.3 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:TSSOP-16 封装:Reel
PI90LV032ALEX 功能描述:总线接收器 Quad LVDS Line Rcvr RoHS:否 制造商:Texas Instruments 接收机数量:4 接收机信号类型:Differential 接口类型:EIA/TIA-422-B, V.11 工作电源电压:3.3 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:TSSOP-16 封装:Reel
PI90LV032ALX 制造商:Pericom Semiconductor Corporation 功能描述:LVDS Receiver 16-Pin TSSOP T/R
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