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| 型号： | PIC10F202T-I/PG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, RISC MICROCONTROLLER, PDIP8 |
| 封装： | 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-8 |
| 文件页数： | 40/88页 |
| 文件大小： | 1127K |
| 代理商： | PIC10F202T-I/PG |
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2004 Microchip Technology Inc.
Preliminary
DS41239A-page 43
PIC10F200/202/204/206
TABLE 9-2:
RESET CONDITION FOR SPECIAL REGISTERS
9.3.1
MCLR ENABLE
This configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
FIGURE 9-1:
MCLR SELECT
9.4
Power-on Reset (POR)
The PIC10F200/202/204/206 devices incorporate an
on-chip
Power-on
Reset
(POR)
circuitry,
which
provides an internal chip Reset for most power-up
situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper oper-
ation. To take advantage of the internal POR, program
the GP3/MCLR/VPP pin as MCLR and tie through a
resistor to VDD, or program the pin as GP3. An internal
weak pull-up resistor is implemented using a transistor
(refer to Table 12-3 for the pull-up resistor ranges).
This will eliminate external RC components usually
needed to create a Power-on Reset. A maximum rise
Characteristics” for details.
When the devices start normal operation (exit the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 9-2.
The Power-on Reset circuit and the Device Reset
Timer (see Section 9.5 “Device Reset Timer (DRT)”)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 18 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low is shown
bringing MCLR high. The chip will actually come out of
Reset TDRT msec after MCLR goes high.
In Figure 9-4, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be GP3). The VDD is stable before
the Start-up timer times out and there is no problem in
getting a proper Reset. However, Figure 9-5 depicts a
problem situation where VDD rises too slowly. The time
between when the DRT senses that MCLR is high and
when MCLR and VDD actually reach their full value, is
too long. In this situation, when the start-up timer times
out, VDD has not reached the VDD (min) value and the
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 9-4).
For additional information, refer to Application Notes
AN522 “Power-Up Considerations”, (DS00522) and
AN607 “Power-up Trouble Shooting”, (DS00607).
STATUS Addr: 03h
PCL Addr: 02h
Power-on Reset
00-1 1xxx
1111 1111
MCLR Reset during normal operation
000u uuuu
1111 1111
MCLR Reset during Sleep
0001 0uuu
1111 1111
WDT Reset during Sleep
0000 0uuu
1111 1111
WDT Reset normal operation
0000 uuuu
1111 1111
Wake-up from Sleep on pin change
1001 0uuu
1111 1111
Wake-up from Sleep on comparator change
0101 0uuu
1111 1111
Legend: u = unchanged, x = unknown, — = unimplemented bit, read as ‘0’.
GP3/MCLR/VPP
MCLRE
Internal MCLR
GPWU
Note:
When the devices start normal operation
(exit the Reset condition), device operat-
ing
parameters
(voltage,
frequency,
temperature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
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