参数资料
型号: PIC10F206-E/P
厂商: Microchip Technology
文件页数: 70/94页
文件大小: 0K
描述: IC PIC MCU FLASH 512X12 8DIP
产品培训模块: Asynchronous Stimulus
标准包装: 60
系列: PIC® 10F
核心处理器: PIC
芯体尺寸: 8-位
速度: 4MHz
外围设备: POR,WDT
输入/输出数: 3
程序存储器容量: 768B(512 x 12)
程序存储器类型: 闪存
RAM 容量: 24 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 8-DIP(0.300",7.62mm)
包装: 管件
配用: AC162059-ND - HEADER INTRFC MPLAB ICD2 8/14PIN
73
AT89/83EB5114
4311C–8051–02/08
Launch the programming of the memory spaces
Get the status of the flash memory (busy/not busy)
Mapping of the Memory Space
By default, the user space is accessed by MOVC instruction for read only. The column
latches space is made accessible by setting the FPS bit in FCON register. Writing is
possible from 0000h to 0FFFh, address bits 6 to 0 are used to select an address within a
page while bits 14 to 7 are used to select the programming address of the page.
The other memory spaces (user, extra row, hardware security) are made accessible in
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-
dance with Table 57. A MOVC instruction is then used for reading these spaces.
Table 57. .FM0 Blocks Select Bits
Launching programming
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the
programming. This sequence is 5xh followed by Axh. Table 33 summarizes the memory
spaces to program according to FMOD1:0 bits.
Figure 33. Programming spaces
Notes: 1. The sequence 5xh and Axh must be executing without instructions between then oth-
erwise the programming is aborted.
2. Interrupts that may occur during programming time must be disable to avoid any spu-
rious exit of the idle mode.
FMOD1
FMOD0
FM0 Adressable space
0
User (0000h-FFFFh)
0
1
Extra Row(FF80h-FFFFh)
1
0
Hardware Security Byte (0000h)
1
reserved
Write to FCON
Operation
FPL3:0
FPS
FMOD1
FMOD0
User
5
X
0
No action
A
X
0
Write the column latches in user
space
Extra Row
5
X
0
1
No action
A
X
0
1
Write the column latches in extra row
space
Hardware
Security
Byte
5
X
1
0
No action
A
X
1
0
Write the fuse bits space
Reserved
5
X
1
No action
A
X
1
No action
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