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参数资料
型号： PIC12C509/JW
厂商： Microchip Technology
文件页数： 105/113页
文件大小： 0K
描述： IC MCU EPROM 1KX12 8CDIP
标准包装： 56
系列： PIC® 12C
核心处理器： PIC
芯体尺寸： 8-位
速度： 4MHz
外围设备： POR，WDT
输入/输出数： 5
程序存储器容量： 1.5KB（1K x 12）
程序存储器类型： EPROM，UV
RAM 容量： 41 x 8
电压 - 电源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
振荡器型： 内部
工作温度： 0°C ~ 70°C
封装/外壳： 8-CDIP（0.300"，7.62mm）窗口
包装： 管件
配用： DVMCPA-ND - KIT DVR BOARD EVAL SYSTEM MXDEV1
DVA12XP080-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
1999 Microchip Technology Inc.
DS40139E-page 91
PIC12C5XX
TABLE 13-8:
EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE5XX
ONLY.
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0
°C ≤ TA ≤ +70°C, Vcc = 3.0V to 5.5V (commercial)
–40
°C ≤ TA ≤ +85°C, Vcc = 3.0V to 5.5V (industrial)
–40
°C ≤ TA ≤ +125°C, Vcc = 4.5V to 5.5V (extended)
Operating Voltage VDD range is described in Section 13.1
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
FCLK
—
100
400
kHz
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
3.0V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Clock high time
THIGH
4000
600
—
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
3.0V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Clock low time
TLOW
4700
1300
—
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
3.0V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
SDA and SCL rise time
(Note 1)
TR
—
1000
300
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
3.0V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
SDA and SCL fall time
TF
—
300
ns
(Note 1)
START condition hold time
THD:STA
4000
600
—
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
3.0V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
START condition setup time
TSU:STA
4700
600
—
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
3.0V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Data input hold time
THD:DAT
0
—
ns
(Note 2)
Data input setup time
TSU:DAT
250
100
—
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
3.0V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
STOP condition setup time
TSU:STO
4000
600
—
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
3.0V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Output valid from clock
(Note 2)
TAA
—
3500
900
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
3.0V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Bus free time: Time the bus must
be free before a new transmis-
sion can start
TBUF
4700
1300
—
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
3.0V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Output fall time from VIH
minimum to VIL maximum
TOF
20+0.1
CB
250
ns
(Note 1), CB
≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
TSP
—
50
ns
(Notes 1, 3)
Write cycle time
TWC
—4
ms
Endurance
1M
—
cycles
25
°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on Microchip’s website.
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