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参数资料
| 型号： | PIC12CE518-04I/SM |
| 厂商： | Microchip Technology |
| 文件页数： | 28/113页 |
| 文件大小： | 0K |
| 描述： | IC MCU OTP 512X12 W/EE 8-SOIC |
| 产品培训模块： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 标准包装： | 90 |
| 系列： | PIC® 12C |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 4MHz |
| 外围设备： | POR，WDT |
| 输入/输出数： | 5 |
| 程序存储器容量： | 768B（512 x 12） |
| 程序存储器类型： | OTP |
| EEPROM 大小： | 16 x 8 |
| RAM 容量： | 25 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.209"，5.30mm 宽） |
| 包装： | 管件 |
| 配用： | XLT08SO-1-ND - SOCKET TRANSITION 8SOIC 150/208 AC164312-ND - MODULE SKT FOR PM3 16SOIC ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING 309-1048-ND - ADAPTER 8-SOIC TO 8-DIP 309-1047-ND - ADAPTER 8-SOIC TO 8-DIP AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
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1999 Microchip Technology Inc.
DS40139E-page 21
PIC12C5XX
5.0
I/O PORT
As with any other register, the I/O register can be
written and read under program control. However, read
instructions (e.g., MOVF GPIO,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers are all
set. See Section 7.0 for SCL and SDA description for
PIC12CE5XX.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP5:GP0). Bits 7 and 6 are unimplemented
and read as '0's. Please note that GP3 is an input only
pin. The configuration word can set several I/O’s to
alternate functions. When acting as alternate functions
the pins will read as ‘0’ during port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also with wake-up on change. The wake-up on
change and weak pull-up functions are not pin
selectable. If pin 4 is configured as MCLR, weak pull-
up is always on and wake-up on change for this pin is
not enabled.
5.2
TRIS Register
The output driver control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected
pins,
enabling
the
output
buffer.
The
exceptions are GP3 which is input only and GP2 which
may be controlled by the option register, see Figure 4-
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
5.3
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is input
only, may be used for both input and output operations.
For input operations these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF
GPIO,W
). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.
FIGURE 5-1:
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
Q
D
Q
CK
Q
D
Q
CK
P
N
WR
Port
TRIS ‘f’
Data
TRIS
RD Port
VSS
VDD
I/O
pin(1,3)
W
Reg
Latch
Reset
(2)
Note 1: I/O pins have protection diodes to VDD
and VSS.
Note 2: See Table 3-1 for buffer type.
Note 3: See Section 7.0 for SCL and SDA
description for PIC12CE5XX
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