参数资料
型号: PIC12F508T-I/SN
厂商: Microchip Technology
文件页数: 21/44页
文件大小: 0K
描述: IC MCU FLASH 512X12 8SOIC
产品培训模块: Asynchronous Stimulus
标准包装: 3,300
系列: PIC® 12F
核心处理器: PIC
芯体尺寸: 8-位
速度: 4MHz
外围设备: POR,WDT
输入/输出数: 5
程序存储器容量: 768B(512 x 12)
程序存储器类型: 闪存
RAM 容量: 25 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
配用: AC162059-ND - HEADER INTRFC MPLAB ICD2 8/14PIN
PIC12F508/509/16F505
DS41236E-page 28
2009 Microchip Technology Inc.
4.9
Indirect Data Addressing: INDF
and FSR Registers
The INDF register
is
not
a physical
register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
4.9.1
INDIRECT ADDRESSING
Register file 07 contains the value 10h
Register file 08 contains the value 0Ah
Load the value 07 into the FSR register
A read of the INDF register will return the value
of 10h
Increment the value of the FSR register by one
(FSR = 08)
A read of the INDR register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although Status bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-1.
EXAMPLE 4-1:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
The FSR is a 5-bit wide register. It is used in conjunction
with the INDF register to indirectly address the data
memory area.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
FIGURE 4-7:
DIRECT/INDIRECT ADDRESSING (PIC12F508/509)
PIC12F508 – Does not use banking. FSR <7:5> are
unimplemented and read as ‘1’s.
PIC12F509 – Uses FSR<5>. Selects between bank 0
and bank 1. FSR<7:6> are unimplemented, read as
‘1’.
PIC16F505 – Uses FSR<6:5>. Selects from bank 0 to
bank 3. FSR<7> is unimplemented, read as ‘1’.
MOVLW
0x10
;initialize pointer
MOVWF
FSR
;to RAM
NEXT
CLRF
INDF
;clear INDF
;register
INCF
FSR,F
;inc pointer
BTFSC
FSR,4
;all done?
GOTO
NEXT
;NO, clear next
CONTINUE
:
;YES, continue
:
Note 1:
For register map detail, see Section 4.3 “Data Memory Organization”.
2:
PIC12F509.
Bank
Location Select
Bank Select
Indirect Addressing
Direct Addressing
Data
Memory(1)
0Fh
10h
Bank 0
Bank 1(2)
0
4
5
6
(FSR)
00
01
00h
1Fh
3Fh
(opcode)
0
4
5
6
(FSR)
Addresses
map back to
addresses
in Bank 0.
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