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参数资料
| 型号： | PIC12F519T-I/MS |
| 厂商： | Microchip Technology |
| 文件页数： | 42/96页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 1KX12 8MSOP |
| 产品培训模块： | Asynchronous Stimulus |
| 标准包装： | 2,500 |
| 系列： | PIC® 12F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 8MHz |
| 外围设备： | POR，WDT |
| 输入/输出数： | 5 |
| 程序存储器容量： | 1.5KB（1K x 12） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 41 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 包装： | 带卷 (TR) |
| 配用： | AC162096-ND - HEADER MPLAB ICD2 PIC16F526 8/14 AC164325-ND - MODULE SKT FOR 8MSOP |
| 其它名称： | PIC12F519T-I/MSTR |
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2008 Microchip Technology Inc.
DS41319B-page 45
PIC12F519
8.5
Device Reset Timer (DRT)
On the PIC12F519 device, the DRT runs any time the
device is powered up. DRT runs from Reset and varies
based on oscillator selection and Reset type (see
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows VDD to rise above VDD min. and
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the devices in a Reset condition after MCLR has
reached a logic high (VIH MCLR) level. Programming
GP3/MCLR/VPP as MCLR and using an external RC
network connected to the MCLR input is not required in
most cases. This allows savings in cost-sensitive and/or
space restricted applications, as well as allowing the
use of the GP3/MCLR/VPP pin as a general purpose
input.
The Device Reset Time delays will vary from
chip-to-chip due to VDD, temperature and process
variation. See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 8.8.2 “Wake-up
from Sleep”, Notes 1, 2 and 3
.
TABLE 8-5:
DRT (DEVICE RESET TIMER
PERIOD)
8.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (GP5)/OSC1/CLKIN pin
and the internal 4 or 8 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The
WDT
can
be
permanently
disabled
by
programming the configuration WDTE as a ‘0’ (see
). Refer to the
PIC12F519 Programming Specification (DS41316) to
determine how to access the Configuration Word.
8.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writing
to the OPTION register. Thus, a time-out period of a
nominal 2.3 seconds can be realized. These periods
vary with temperature, VDD and part-to-part process
variations (see DC specs).
Under worst-case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
8.6.2
WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
Oscillator
Configuration
POR Reset
Subsequent
Resets
INTOSC, EXTRC
1 ms (typical)
10
μs (typical)
LP, XT
18 ms (typical)
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