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参数资料
| 型号： | PIC12F519T-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 44/96页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 1KX12 8SOIC |
| 产品培训模块： | Asynchronous Stimulus |
| 标准包装： | 3,300 |
| 系列： | PIC® 12F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 8MHz |
| 外围设备： | POR，WDT |
| 输入/输出数： | 5 |
| 程序存储器容量： | 1.5KB（1K x 12） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 41 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 其它名称： | PIC12F519T-I/SNTR |
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2008 Microchip Technology Inc.
DS41319B-page 47
PIC12F519
8.7
Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO, PD, GPWUF)
The TO, PD and (GPWUF) bits in the STATUS register
can be tested to determine if a Reset condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) Reset.
TABLE 8-7:
TO/PD/(GPWUF) STATUS
AFTER RESET
8.8
Power-down Mode (Sleep)
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep).
8.8.1
SLEEP
The Power-down mode is entered by executing a
SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
GP3/MCLR/VPP pin must be at a logic high level if
MCLR is enabled.
8.8.2
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
5.
An external Reset input on GP3/MCLR/VPP pin,
when configured as MCLR.
6.
A Watchdog Timer Time-out Reset (if WDT was
enabled).
7.
A change on input pin GP0, GP1 and GP3 when
wake-up on change is enabled.
These events cause a device Reset. The TO, PD and
GPWUF bits can be used to determine the cause of
device Reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The GPWUF bit indicates a change in state while in
Sleep at pins GP0, GP1 and GP3 (since the last file or
bit operation on GPIO port).
The WDT is cleared when the device wakes from
Sleep, regardless of the wake-up source.
GPWUF
TO
PD
Reset Caused By
00
0
WDT wake-up from Sleep
00
u
WDT time-out (not from
Sleep)
01
0
MCLR wake-up from Sleep
01
1
Power-up
0u
u
MCLR not during Sleep
11
0
Wake-up from Sleep on pin
change
Legend: u
= unchanged
Note 1:
The TO, PD and GPWUF bits maintain
their status (u) until a Reset occurs. A
low-pulse on the MCLR input does not
change the TO, PD and GPWUF Status
bits.
Note:
A Reset generated by a WDT time-out
does not drive the MCLR pin low.
Note:
Caution:
Right before entering Sleep,
read the input pins. When in Sleep, wake
up occurs when the values at the pins
change from the state they were in at the
last reading. If a wake-up on change
occurs and the pins are not read before
re-entering Sleep, a wake-up will occur
immediately even if no pins change while
in Sleep mode.
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