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参数资料
| 型号： | PIC12F629-I/MD |
| 厂商： | Microchip Technology |
| 文件页数： | 8/35页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 1KX14 8DFN |
| 产品培训模块： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 标准包装： | 91 |
| 系列： | PIC® 12F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 外围设备： | POR，WDT |
| 输入/输出数： | 5 |
| 程序存储器容量： | 1.75KB（1K x 14） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 128 x 8 |
| RAM 容量： | 64 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-VDFN 裸露焊盘 |
| 包装： | 管件 |
| 产品目录页面： | 637 (CN2011-ZH PDF) |
| 配用： | AC164326-ND - MODULA SKT PM3 20QFN |
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16
0787E–MICRO–3/06
AT89S53
Figure 9. SPI Transfer Format with CPHA = 1
*Not defined but normally LSB of previously transmitted character
Interrupts
The AT89S53 has a total of six interrupt vectors: two exter-
nal interrupts (INT0 and INT1), three timer interrupts
(Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 10.
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
Note that Table 10 shows that bit position IE.6 is unimple-
men t ed. In the AT89C51 , bit p o sition IE .5 is also
unimplemented. User software should not write 1s to these
bit positions, since they may be used in future AT89
products.
Figure 10. Interrupt Sources
MSB
6
5
4
3
2
1
LSB
1
2
3
4
5
6
7
8
MSB
*
65
4
3
2
1
LSB
SCK CYCLE #
(FOR REFERENCE)
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
SS (TO SLAVE)
Table 10. Interrupt Enable (IE) Register
(MSB)(LSB)
EA
–
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol
Position
Function
EA
IE.7
Disables all interrupts. If EA = 0, no interrupt
is acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit.
–
IE.6
Reserved.
ET2
IE.5
Timer 2 interrupt enable bit.
ES
IE.4
SPI and UART interrupt enable bit.
ET1
IE.3
Timer 1 interrupt enable bit.
EX1
IE.2
External interrupt 1 enable bit.
ET0
IE.1
Timer 0 interrupt enable bit.
EX0
IE.0
External interrupt 0 enable bit.
User software should never write 1s to unimplemented bits, because
they may be used in future AT89 products.
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