参数资料
型号: PIC12F683-I/MD
厂商: Microchip Technology
文件页数: 9/176页
文件大小: 0K
描述: IC PIC MCU FLASH 2KX14 8DFN
产品培训模块: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
Digi-Key 应用说明: AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
标准包装: 91
系列: PIC® 12F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 5
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-VDFN 裸露焊盘
包装: 管件
产品目录页面: 645 (CN2011-ZH PDF)
配用: AC164326-ND - MODULA SKT PM3 20QFN
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
PIC12F683
DS41211D-page 104
2007 Microchip Technology Inc.
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BTFSS f,b
Operands:
0
≤ f ≤ 127
0
≤ b < 7
Operation:
skip if (f<b>) = 1
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP
is executed instead, making this a
2-cycle instruction.
CALL
Call Subroutine
Syntax:
[ label ] CALL k
Operands:
0
≤ k ≤ 2047
Operation:
(PC)+ 1
→ TOS,
k
→ PC<10:0>,
(PCLATH<4:3>)
→ PC<12:11>
Status Affected:
None
Description:
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL
is a two-cycle instruction.
CLRF
Clear f
Syntax:
[ label ] CLRF
f
Operands:
0
≤ f ≤ 127
Operation:
00h
→ (f)
1
→ Z
Status Affected:
Z
Description:
The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h
→ (W)
1
→ Z
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z)
is set.
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
00h
→ WDT
0
→ WDT prescaler,
1
→ TO
1
→ PD
Status Affected:
TO, PD
Description:
CLRWDT
instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
COMF
Complement f
Syntax:
[ label ] COMF
f,d
Operands:
0
≤ f ≤ 127
d
∈ [0,1]
Operation:
(f)
→ (destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
DECF
Decrement f
Syntax:
[ label ] DECF f,d
Operands:
0
≤ f ≤ 127
d
∈ [0,1]
Operation:
(f) - 1
→ (destination)
Status Affected:
Z
Description:
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
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