参数资料
型号: PIC16C433T-E/SO
厂商: Microchip Technology
文件页数: 26/126页
文件大小: 0K
描述: IC MCU CMOS 8BIT 10MHZ 2K 18SOIC
标准包装: 1,100
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 10MHz
连通性: LIN(本地互连网络)
外围设备: POR,WDT
输入/输出数: 5
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: OTP
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 18-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
121
4378C–AVR–09/08
AT90PWM1
15.10.7
Input Capture Register 1 – ICR1H and ICR1L
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
15.10.8
Timer/Counter1 Interrupt Mask Register – TIMSK1
Bit 7, 6 – Res: Reserved Bits
These bits are unused bits in the AT90PWM1, and will always read as zero.
Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
when the ICF1 Flag, located in TIFR1, is set.
Bit 4, 3 – Res: Reserved Bits
These bits are unused bits in the AT90PWM1, and will always read as zero.
Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
executed when the OCF1B Flag, located in TIFR1, is set.
Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
executed when the OCF1A Flag, located in TIFR1, is set.
Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
the TOV1 Flag, located in TIFR1, is set.
Bit
7
65
43
21
0
ICR1[15:8]
ICR1H
ICR1[7:0]
ICR1L
Read/Write
R/W
Initial Value0
00
0
Bit
7
65
43
2
1
0
ICIE1
OCIE1B
OCIE1A
TOIE1
TIMSK1
Read/Write
R
R/W
R
R/W
Initial Value
0
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