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参数资料
型号： PIC16C472
厂商： Microchip Technology Inc.
英文描述： 14-Pin, 8-Bit CMOS OTP Microcontroller With A/D Converter(工作电压2.5~5.5V，捕捉/比较/PWM的微控制器)
中文描述： 14引脚，8位微控制器的CMOS检察官办公室的A / D转换器（工作电压2.5?5.5V之间，捕捉/比较/脉宽调制的微控制器）
文件页数： 17/170页
文件大小： 4191K
代理商： PIC16C472
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 15
PIC16F62X
3.2.2
SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 3-1). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 3-1:
SPECIAL REGISTERS SUMMARY BANK 0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset
(1)
Details
on Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
25
01h
TMR0
Timer0 Module’s Register
43
02h
PCL
Program Counter's (PC) Least Significant Byte
13
03h
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
19
04h
FSR
Indirect data memory address pointer
xxxx xxxx
xxxx 0000
xxxx xxxx
25
05h
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
29
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
34
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
0Ah
PCLATH
—
—
—
Write buffer for upper 5 bits of program counter
---0 0000
0000 000x
0000 -000
25
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
21
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
23
0Dh
—
Unimplemented
—
—
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1
xxxx xxxx
xxxx xxxx
46
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1
46
10h
T1CON
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
0000 0000
-000 0000
46
11h
TMR2
TMR2 module’s register
50
12h
T2CON
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
50
13h
—
Unimplemented
—
—
14h
—
Unimplemented
—
—
15h
CCPR1L
Capture/Compare/PWM register (LSB)
xxxx xxxx
xxxx xxxx
--00 0000
0000 -00x
0000 0000
0000 0000
61
16h
CCPR1H
Capture/Compare/PWM register (MSB)
61
17h
CCP1CON
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
61
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
67
19h
TXREG
USART Transmit data register
74
1Ah
RCREG
USART Receive data register
77
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
—
Unimplemented
—
—
1Fh
Legend:
CMCON
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000
53
Note
1:
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