参数资料
型号: PIC16C64A-10/PT
厂商: Microchip Technology
文件页数: 43/126页
文件大小: 0K
描述: IC MCU OTP 2KX14 PWM 44TQFP
产品培训模块: Asynchronous Stimulus
标准包装: 160
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 10MHz
连通性: I²C,SPI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 33
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: OTP
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 6 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 44-TQFP
包装: 托盘
1997 Microchip Technology Inc.
DS30234D-page 23
PIC16C6X
4.2.2
SPECIAL FUNCTION REGISTERS:
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The special function registers can be classied into two
sets (core and peripheral). The registers associated
with the “core” functions are described in this section
and those related to the operation of the peripheral fea-
tures are described in the section of that peripheral fea-
ture.
TABLE 4-1:
SPECIAL FUNCTION REGISTERS FOR THE PIC16C61
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR
Value on
all other
resets(3)
Bank 0
00h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
02h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
03h(1)
STATUS
IRP(4)
RP1(4)
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
04h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
05h
PORTA
PORTA Data Latch when written: PORTA pins when read
---x xxxx
---u uuuu
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
uuuu uuuu
07h
Unimplemented
08h
Unimplemented
09h
Unimplemented
0Ah(1,2)
PCLATH
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0Bh(1)
INTCON
GIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0-00 000x
0-00 000u
Bank 1
80h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
83h(1)
STATUS
IRP(4)
RP1(4)
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
84h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRISA
PORTA Data Direction Register
---1 1111
86h
TRISB
PORTB Data Direction Control Register
1111 1111
87h
Unimplemented
88h
Unimplemented
89h
Unimplemented
8Ah(1,2)
PCLATH
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh(1)
INTCON
GIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0-00 000x
0-00 000u
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented locations read as '0'.
Shaded locations are unimplemented and read as ‘0’
Note 1:
These registers can be addressed from either bank.
2:
The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose con-
tents are transferred to the upper byte of the program counter. (PC<12:8>)
3:
Other (non power-up) resets include external reset through MCLR and the Watchdog Timer Reset.
4:
The IRP and RP1 bits are reserved on the PIC16C61, always maintain these bits clear.
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