参数资料
型号: PIC16C64A-10E/P
厂商: Microchip Technology
文件页数: 55/126页
文件大小: 0K
描述: IC MCU OTP 2KX14 PWM 40DIP
标准包装: 10
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 10MHz
连通性: I²C,SPI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 33
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: OTP
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 6 V
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
PIC16C6X
DS30234D-page 34
1997 Microchip Technology Inc.
Bank 2
100h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
101h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
102h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
103h(1)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
104h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
105h
Unimplemented
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
uuuu uuuu
107h
Unimplemented
108h
Unimplemented
109h
Unimplemented
10Ah(1,2) PCLATH
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
10Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
10Ch-
10Fh
Unimplemented
Bank 3
180h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
181h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
182h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
183h(1)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
184h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
185h
Unimplemented
186h
TRISB
PORTB Data Direction Register
1111 1111
187h
Unimplemented
188h
Unimplemented
189h
Unimplemented
18Ah(1,2) PCLATH
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
18Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
18Ch-
19Fh
Unimplemented
TABLE 4-6:
SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
These registers can be addressed from any bank.
2:
The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3:
Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4:
PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
5:
PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
6:
PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.
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