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参数资料
型号： PIC16C710-20I/SS
厂商： Microchip Technology
文件页数： 175/177页
文件大小： 0K
描述： IC MCU OTP 512X14 A/D 20SSOP
产品培训模块： Asynchronous Stimulus
标准包装： 67
系列： PIC® 16C
核心处理器： PIC
芯体尺寸： 8-位
速度： 20MHz
外围设备： 欠压检测/复位，POR，WDT
输入/输出数： 13
程序存储器容量： 896B（512 x 14）
程序存储器类型： OTP
RAM 容量： 36 x 8
电压 - 电源 (Vcc/Vdd)： 4 V ~ 6 V
数据转换器： A/D 4x8b
振荡器型： 外部
工作温度： -40°C ~ 85°C
封装/外壳： 20-SSOP（0.209"，5.30mm 宽）
包装： 管件
配用： 309-1016-ND - ADAPTER 20-SSOP TO 18-DIP
97
7593L–AVR–09/12
AT90USB64/128
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
clk_I/O/2.5.
An external clock source can not be prescaled.
Figure 13-2. Prescaler for synchronous Timer/Counters
13.4
GTCCR – General Timer/Counter Control Register
Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-
ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared
by hardware, and the Timer/Counters start counting simultaneously.
Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters
When this bit is one, Timer/Counter0 and Timer/Counter1 and Timer/Counter3 prescaler will be
Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note
that Timer/Counter0, Timer/Counter1 and Timer/Counter3 share the same prescaler and a reset
of this prescaler will affect all timers.
PSR10
Clear
Tn
clk
I/O
Synchronization
TIMER/COUNTERn CLOCK SOURCE
clk
Tn
TIMER/COUNTERn CLOCK SOURCE
clk
Tn
CSn0
CSn1
CSn2
CSn0
CSn1
CSn2
Bit
7
6
5
4
3
2
1
0
TSM
–
PSRASY
PSRSYNC
GTCCR
Read/write
R/W
R
R/W
Initial value
0
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