
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 61
PIC16C925/926
9.1
SPI Mode
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
Serial Data Out (SDO) RC5/SDO
Serial Data In (SDI) RC4/SDI
Serial Clock (SCK) RC3/SCK
Additionally, a fourth pin may be used when in a Slave
mode of operation:
Slave Select (SS) RA5/AN4/SS
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock Edge (output data on rising/falling edge of
SCK)
Clock Rate (Master mode only)
Slave Select mode (Slave mode only)
The SSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register.
Then,
the
buffer
full
detect
bit,
BF
(SSPSTAT<0>),
and
interrupt
flag
bit,
SSPIF
(PIR1<3>), are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON<7>), will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the
SSPBUF register completed successfully. When the
application software is expecting to receive valid data,
the SSPBUF should be read before the next byte of
data to transfer is written to the SSPBUF. Buffer full bit,
BF (SSPSTAT<0>), indicates when SSPBUF has been
loaded with the received data (transmission is com-
plete). When the SSPBUF is read, bit BF is cleared.
This data may be irrelevant if the SPI is only a transmit-
ter. Generally, the SSP interrupt is used to determine
when the transmission/reception has completed. The
SSPBUF must be read and/or written. If the interrupt
method is not going to be used, then software polling
can be done to ensure that a write collision does not
(SSPSR) for data transmission. The MOVWF RXDATA
instruction (shaded) is only required if the received data
is meaningful.
EXAMPLE 9-1:
LOADING THE SSPBUF
(SSPSR) REGISTER
The block diagram of the SSP module, when in SPI
directly readable or writable, and can only be accessed
from addressing the SSPBUF register. Additionally, the
SSP status register (SSPSTAT) indicates the various
status conditions.
FIGURE 9-1:
SSP BLOCK DIAGRAM
(SPI MODE)
BCF
STATUS, RP1
;Select Bank1
BSF
STATUS, RP0
;
LOOP
BTFSS SSPSTAT, BF
;Has data been
;received
;(transmit
;complete)?
GOTO
LOOP
;No
BCF
STATUS, RP0
;Select Bank0
MOVF
SSPBUF, W
;W reg = contents
;of SSPBUF
MOVF
TXDATA, W
;W reg = contents
; of TXDATA
MOVWF SSPBUF
;New data to xmit
MOVWF RXDATA
;Save in user RAM
Read
Write
Internal
Data Bus
RC4/SDI/SDA
RC5/SDO
RA5/AN4/SS
RC3/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0
Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TCY
Prescaler
4, 16, 64
TRISC<3>
2
Edge
Select
2
4
SCL