参数资料
型号: PIC16F1526T-I/MR
厂商: Microchip Technology
文件页数: 13/94页
文件大小: 0K
描述: MCU 14KB FLASH 768B RAM 64-QFN
标准包装: 3,300
系列: PIC® XLP™ 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 54
程序存储器容量: 14KB(8K x 14)
程序存储器类型: 闪存
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 2.3 V ~ 5.5 V
数据转换器: A/D 30x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-VFQFN 裸露焊盘
包装: 带卷 (TR)
182
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
19.8
Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
19.8.1
Asynchronous Clock Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 19-5
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-
izontal arrows illustrate the synchronization variation due to the sampling process. Note the
larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples
denoted zero are samples done when the RxDn line is idle (i.e., no communication activity).
Figure 19-5. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the
start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in
the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-
ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the
figure), to decide if a valid start bit is received. If two or more of these three samples have logical
high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts
looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-
ery logic is synchronized and the data recovery can begin. The synchronization process is
repeated for each start bit.
19.8.2
Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data
recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight
states for each bit in Double Speed mode. Figure 19-6 shows the sampling of the data bits and
the parity bit. Each of the samples is given a number that is equal to the state of the recovery
unit.
12
34
56
7
8
9
10
11
12
13
14
15
16
12
START
IDLE
0
BIT 0
3
123
4
5
678
12
0
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
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PIC16F1527-I/MR 制造商:Microchip Technology Inc 功能描述:IC 8BIT MCU PIC16F 20 MHz 64-QFN 制造商:Microchip Technology Inc 功能描述:IC, 8BIT MCU, PIC16F, 20 MHz, 64-QFN; Controller Family/Series:PIC16F; Core Size:8bit; No. of I/O's:54; Program Memory Size:28KB; RAM Memory Size:1536Byte; CPU Speed:20MHz; Oscillator Type:External, Internal; No. of Timers:9 ;RoHS Compliant: No
PIC16F1527-I/PT 功能描述:8位微控制器 -MCU 14KB Flash RAM 768b nanoWatt RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT