参数资料
型号: PIC16F526-I/MG
厂商: Microchip Technology
文件页数: 15/21页
文件大小: 0K
描述: MCU PIC 1.5K FLASH 3X3 16QFN
产品培训模块: 8-bit PIC® Microcontroller Portfolio
标准包装: 120
系列: PIC® 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: POR,WDT
输入/输出数: 11
程序存储器容量: 1.5KB(1K x 12)
程序存储器类型: 闪存
RAM 容量: 67 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 3x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 16-VFQFN 裸露焊盘
包装: 托盘
产品目录页面: 638 (CN2011-ZH PDF)
2007 Microchip Technology Inc.
DS41317B-page 3
PIC16F526
3.0
COMMANDS AND
ALGORITHMS
3.1
Program/Verify Mode
The Program/Verify mode is entered by holding pins
ICSPCLK and ICSPDAT low while raising VDD pin from
VIL to VDD. Then raise VPP from VIL to VIHH. Once in
this mode, the user program memory and configuration
memory can be accessed and programmed in serial
fashion. Clock and data are Schmitt Trigger input in this
mode.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at VIL). This means
that all I/Os are in the Reset state (high-impedance
inputs).
3.1.1
PROGRAMMING
The programming sequence loads a word, programs,
verifies and finally increments the PC.
Program/Verify mode entry will set the address to
0x7FF. The Increment Address command will
increment the PC. The available commands are shown
FIGURE 3-1:
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
3.1.2
SERIAL PROGRAM/VERIFY
OPERATION
The RB1 pin is used as a clock input pin, and the RB0
pin is used for entering command bits and data input/
output during serial operation. To input a command, the
clock pin (RB1) is cycled 6 times. Each command bit is
latched on the falling edge of the clock with the Least
Significant bit (LSb) of the command being input first.
The data on pin RB0 is required to have a minimum
setup and hold time of 100 ns with respect to the falling
edge of the clock. Commands that have data associ-
ated with them (Read and Load) are specified to have
a minimum delay of 1 s between the command and
the data. After this delay the clock pin is cycled 16 times
with the first cycle being a Start bit and the last cycle
being a Stop bit. Data is also input and output LSb first,
with data input being latched on the falling edge of the
clock and data output being driven on the rising edge of
the clock. Therefore, during a Read operation the LSb
will be transmitted onto pin RB0 on the rising edge of
the second cycle, and during a Load operation the LSb
will be latched on the falling edge of the second cycle.
A minimum 1 s delay is also specified between con-
secutive commands; except the “End Programming”
command which requires a 100 s delay. Because this
is a 12-bit core, the two MSbs of the data word are
ignored. The commands that are available are
described in Table 3-1.
TABLE 3-1:
COMMAND MAPPING LOAD DATA
VPP
THLD0
VDD
TPPDP
RB1
(ICSPCLK)
(ICSPDAT)
RB0
Command
Mapping
(MSb ... LSb)
Hex
Value
Data
Load Data
X X 0 0 1 0
2
start_bit, data (14), stop_bit
Read Data
X X 0 1 0 0
4
start_bit, data (14), stop_bit
Increment Address
X X 0 1 1 0
6
Begin Programming
X X 1 0 0 0
8
End Programming
X X 1 1 1 0
E
Bulk Erase Program Memory
X X 1 0 0 1
9
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