参数资料
型号: PIC16F636-E/P
厂商: Microchip Technology
文件页数: 3/74页
文件大小: 0K
描述: IC MCU FLASH 2KX14 14DIP
产品培训模块: Asynchronous Stimulus
标准包装: 30
系列: PIC® 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,LVD,POR,WDT
输入/输出数: 11
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 14-DIP(0.300",7.62mm)
包装: 管件
配用: AC164039-ND - MODULE SKT PROMATE II 20DIP/SOIC
AC162057-ND - MPLAB ICD 2 HEADER 14DIP
ACICE0207-ND - MPLABICE 14P 300 MIL ADAPTER
Micrel, Inc.
KSZ8841-PMQL
October 2007
11
M9999-100407-1.5
Pin
Number
Pin
Name
Type
Pin Function
45
RXP1
I/O
Physical receive (MDI) or transmit (MDIX)signal (+ differential)
46
RXM1
I/O
Physical receive (MDI) or transmit (MDIX) signal (– differential)
47
AGND
Gnd
Analog ground
48
TXP1
I/O
Physical transmit (MDI) or receive (MDIX) signal (+ differential)
49
TXM1
I/O
Physical transmit (MDI) or receive (MDIX) signal (– differential)
50
VDDATX
P
3.3V analog VDD
51
VDDARX
P
3.3V analog VDD
52
NC
No connect
53
NC
No connect
54
AGND
Gnd
Analog ground
55
NC
No connect
56
NC
No connect
57
VDDA
P
1.2 analog VDD
58
AGND
Gnd
Analog ground
59
NC
No connect
60
NC
No connect
61
ISET
O
Set physical transmit output current
Pull-down this pin with a 3.01K 1% resistor to ground.
62
AGND
Gnd
Analog ground
63
VDDAP
P
1.2V analog VDD for PLL
64
AGND
Gnd
Analog ground
65
X1
I
66
X2
O
25MHz crystal/oscillator clock connections
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V
tolerant oscillator and X2 is no connected.
Note: Clock is
50ppm for both crystal and oscillator.
67
RSTN
Ipu
Hardware Reset, Active Low
RSTN will cause the KSZ8841-PMQL to reset all of its functional blocks. RSTN must be
asserted for a minimum duration of 10 ms.
68
PAR
I/O
PCI Parity
Even parity computed for PAD[31:0] and CBE[3:0]N, master drives PAR for address
and write data phase, target drives PAR for read data phase.
69
FRAMEN
I/O
PCI Cycle Frame
This signal is asserted low to indicate the beginning of the address phase of the bus
transaction and de-asserted before the final transfer of the data phase of the
transaction in a bus master mode. As a target, the device monitors this signal before
decoding the address to check if the current transaction is addressed to it.
70
IRDYN
I/O
PCI Initiator Ready
As a bus master, this signal is asserted low to indicate valid data phases on PAD[31:0]
during write data phases, indicates it is ready to accept data during read data phases.
As a target, it’ll monitor this IRDYN signal that indicates the master has put the data on
the bus.
71
TRDYN
I/O
PCI Target Ready
As a bus target, this signal is asserted low to indicate valid data phases on PAD[31:0]
during read data phases, indicates it is ready to accept data during write data phases.
As a master, it will monitor this TRDYN signal that indicates the target is ready for data
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