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参数资料
| 型号： | PIC16F688-E/ML |
| 厂商： | Microchip Technology |
| 文件页数： | 10/204页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 4KX14 16QFN |
| 产品培训模块： | Asynchronous Stimulus |
| 标准包装： | 91 |
| 系列： | PIC® 16F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | UART/USART |
| 外围设备： | 欠压检测/复位，POR，WDT |
| 输入/输出数： | 12 |
| 程序存储器容量： | 7KB（4K x 14） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 256 x 8 |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 数据转换器： | A/D 8x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 包装： | 管件 |
| 配用： | AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN XLT16QFN1-ND - SOCKET TRANSITION 14DIP TO 16QFN AC162061-ND - HEADER INTRFC MPLAB ICD2 20PIN AC162056-ND - HEADER INTERFACE ICD2 16F688 |
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2009 Microchip Technology Inc.
DS41203E-page 105
PIC16F688
10.4.1.5
Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT and TX/
CK pin output drivers are automatically disabled when
the EUSART is configured for synchronous master
receive operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the char-
acter is automatically transferred to the two character
receive FIFO. The Least Significant eight bits of the top
character in the receive FIFO are available in RCREG.
The RCIF bit remains set as long as there are un-read
characters in the receive FIFO.
10.4.1.6
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
10.4.1.7
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
10.4.1.8
Synchronous Master Reception Set-
up:
1.
Initialize the SPBRGH, SPBRG register pair for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3.
Ensure bits CREN and SREN are clear.
4.
If using interrupts, set the GIE and PEIE bits of
the INTCON register and set RCIE.
5.
If 9-bit reception is desired, set bit RX9.
6.
Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
7.
Interrupt flag bit RCIF will be set when reception
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
8.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9.
Read the 8-bit received data by reading the
RCREG register.
10. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PIC16F688-I/ML | 功能描述:8位微控制器 -MCU 7KB 256 RAM 12I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16F688-I/P | 功能描述:8位微控制器 -MCU 7KB 256 RAM 12 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16F688-I/P | 制造商:Microchip Technology Inc 功能描述:IC 8BIT FLASH MCU 16F688 DIP14 |
| PIC16F688-I/P | 制造商:Microchip Technology Inc 功能描述:IC 8BIT FLASH MCU 16F688 DIP14 制造商:Microchip Technology Inc 功能描述:IC, 8BIT FLASH MCU, 16F688, DIP14 制造商:Microchip Technology Inc 功能描述:IC, 8BIT FLASH MCU, 16F688, DIP14; Controller Family/Series:PIC16F; Core Size:8bit; No. of I/O's:12; Supply Voltage Min:2V; Supply Voltage Max:5.5V; Digital IC Case Style:DIP; No. of Pins:14; Program Memory Size:4Kwords; EEPROM ;RoHS Compliant: Yes |
| PIC16F688-I/P-ND | 制造商:Microchip Technology Inc 功能描述: |
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