参数资料
型号: PIC16F72-I/SP
厂商: Microchip Technology
文件页数: 61/136页
文件大小: 0K
描述: IC PIC MCU FLASH 2KX14 28DIP
产品培训模块: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
标准包装: 15
系列: PIC® 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 22
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 5.5 V
数据转换器: A/D 5x8b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 28-DIP(0.300",7.62mm)
包装: 管件
产品目录页面: 639 (CN2011-ZH PDF)
PIC16F72
DS39597C-page 28
2007 Microchip Technology Inc.
4.3
Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
4.4
Prescaler
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
Timer0 module means that there is no prescaler for the
Watchdog Timer, and vice-versa. This prescaler is not
readable or writable (see Figure 4-1).
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF
1,x
....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
TABLE 4-1:
REGISTERS ASSOCIATED WITH TIMER0
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count but will not change the prescaler
assignment.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
01h,101h
TMR0
Timer0 Module Register
xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
TMR0IE INTE
RBIE TMR0IF
INTF
RBIF
0000 000x 0000 000u
81h,181h
OPTION RBPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
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