参数资料
型号: PIC16F870-E/SP
厂商: Microchip Technology
文件页数: 6/143页
文件大小: 0K
描述: IC MCU CMOS 20MHZ 2K FLASH 28DIP
产品培训模块: Asynchronous Stimulus
标准包装: 15
系列: PIC® 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
连通性: UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 22
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
EEPROM 大小: 64 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 5.5 V
数据转换器: A/D 5x10b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 28-DIP(0.300",7.62mm)
包装: 管件
配用: I3-DB16F871-ND - BOARD DAUGHTER ICEPIC3
2003 Microchip Technology Inc.
DS30569B-page 101
PIC16F870/871
FIGURE 11-11:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
11.14 In-Circuit Debugger
When the DEBUG bit in the configuration word is pro-
grammed to a '0', the In-Circuit Debugger functionality
is enabled. This function allows simple debugging func-
tions when used with MPLAB ICD. When the micro-
controller has this feature enabled, some of the
resources are not available for general use. Table 11-8
shows
which
features
are
consumed
by
the
background debugger.
TABLE 11-8:
DEBUGGER RESOURCES
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip, or one of
the third party development tool companies.
11.15 Program Verification/Code
Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
11.16 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 Least Significant bits of the ID
location are used.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKO(4)
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC
PC+1
PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency(2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2
0004h
0005h
Dummy cycle
TOST(2)
PC+2
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Osc mode.
3: GIE = 1 assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
4: CLKO is not available in these Osc modes, but shown here for timing reference.
I/O pins
RB6, RB7
Stack
1 level
Program Memory
Address 0000h must be NOP
Last 100h words
Data Memory
0x070 (0x0F0, 0x170, 0x1F0)
0x1EB - 0x1EF
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