参数资料
型号: PIC16F872T-I/SS
厂商: Microchip Technology
文件页数: 126/167页
文件大小: 0K
描述: IC MCU FLASH 2KX14 EE 28SSOP
产品培训模块: Asynchronous Stimulus
标准包装: 2,100
系列: PIC® 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 22
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
EEPROM 大小: 64 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 5.5 V
数据转换器: A/D 5x10b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
包装: 带卷 (TR)
61
8048C–AVR–02/12
ATtiny43U
If low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
10.3.2
GIMSK – General Interrupt Mask Register
Bits 7, 3:0 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-
ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even
if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from the INT0 Interrupt Vector.
Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT[15:8] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT[15:8] pins are enabled individually by the PCMSK1 Register.
Bit 4 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT[7:0] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK0 Register.
10.3.3
GIFR – General Interrupt Flag Register
Bits 7, 3:0 – Res: Reserved Bits
These bits are reserved and will always read zero.
Table 10-2.
Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request asynchronously
0
1
Any logical change on INT0 generates an interrupt request asynchronously
1
0
The falling edge of INT0 generates an interrupt request asynchronously
1
The rising edge of INT0 generates an interrupt request asynchronously
Bit
7
6
543
21
0
INT0
PCIE1
PCIE0
GIMSK
Read/Write
R
R/W
R
Initial Value
0
Bit
7
6
543
21
0
INTF0
PCIF1
PCIF0
––
GIFR
Read/Write
R
R/W
R
Initial Value
0
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