参数资料
型号: PIC16F886T-I/SS
厂商: Microchip Technology
文件页数: 14/16页
文件大小: 0K
描述: IC PIC MCU FLASH 8KX14 28SSOP
产品培训模块: Asynchronous Stimulus
标准包装: 2,100
系列: PIC® 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 24
程序存储器容量: 14KB(8K x 14)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 368 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 11x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
包装: 带卷 (TR)
配用: DM164123-ND - KIT MANAGEMENT SYSTEM PICDEM
2009 Microchip Technology Inc.
DS80302F-page 7
PIC16F88X
6.
Module: MSSP (I2C Master Mode)
When the MSSP is I2C Master mode with a
slave device stretching the clock, the clock
generation does not function as described in the
data sheet.
When a slave device is performing clock stretching
by pulling the SCL line low, the master device
should continuously sample the SCL line to
determine when all slaves have released SCL.
When SCL is released, the master device should
wait one BRG period to ensure a constant SCL
high time.
The current implementation does not ensure
accurate SCL high time. During clock stretch, the
MSSP device will erroneously continue running
the BRG counter. At the end of the clock stretch
the BRG counter continues to count down for the
remainder of the BRG period, and then the MSSP
device will immediately resume transmitting the
data.
Figure 1 illustrates an expected I2C transmission
in which the SCL line is completely controlled by
the master device and the slave device does not
attempt to stretch the clock period.
Figure 2 illustrates the expected operation of an
I2C transmission in which the slave device has
stretched the clock period by holding the SCL line
low. The high time of the SCL pulse is constant,
regardless of the duration of the clock stretch.
Figure 3 and Figure 4 illustrate an actual I2C
transmission in which the slave has stretched the
clock period by holding the SCL line low. Note that
the high time of the SCL signal has shortened from
the expected time.
FIGURE 1:
ACTUAL (CORRECT) OPERATION WITHOUT CLOCK STRETCHING
FIGURE 2:
EXPECTED OPERATION WITH CLOCK STRETCHING
BRG Period
SDA
SCL
Master
Slave
BRG Period
SDA
SCL
Master
Slave
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