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参数资料
| 型号： | PIC16HV616T-I/SL |
| 厂商： | Microchip Technology |
| 文件页数： | 6/44页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 2KX14 14SOIC |
| 产品培训模块： | Asynchronous Stimulus |
| 标准包装： | 2,600 |
| 系列： | PIC® 16F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 外围设备： | 欠压检测/复位，POR，WDT |
| 输入/输出数： | 11 |
| 程序存储器容量： | 3.5KB（2K x 14） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 128 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 5 V |
| 数据转换器： | A/D 8x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 配用： | AC162083-ND - HEADER MPLAB ICD2 PIC16F616 8/14 XLT14SO-1-ND - SOCKET TRANSITION 14SOIC 150/208 |
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PIC16F610/616/16HV610/616
DS41288F-page 14
2009 Microchip Technology Inc.
2.2
Data Memory Organization
The data memory (see Figure 2-4) is partitioned into
two banks, which contain the General Purpose
Registers (GPR) and the Special Function Registers
(SFR). The Special Function Registers are located in
the
first
32
locations
of
each
bank.
PIC16F610/16HV610 Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented
as
static
RAM.
PIC16F616/16HV616
Register
locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1
are General Purpose Registers, implemented as static
RAM. Register locations F0h-FFh in Bank 1 point to
addresses 70h-7Fh in Bank 0. All other RAM is
unimplemented and returns ‘0’ when read. The RP0 bit
of the STATUS register is the bank select bit.
RP0
0
→ Bank 0 is selected
1
→ Bank 1 is selected
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC16F610/16HV610
and
128 x 8
in
the
PIC16F616/16HV616. Each register is accessed,
either directly or indirectly, through the File Select Reg-
ister (FSR) (see Section 2.4 “Indirect Addressing,
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
Note:
The IRP and RP1 bits of the STATUS
register are reserved and should always be
maintained as ‘0’s.
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