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参数资料
型号： PIC16LC554T-04/SS
厂商： Microchip Technology
文件页数： 51/108页
文件大小： 0K
描述： IC MCU OTP 512X14 20SSOP
产品培训模块： Asynchronous Stimulus
标准包装： 1,600
系列： PIC® 16C
核心处理器： PIC
芯体尺寸： 8-位
速度： 4MHz
外围设备： POR，WDT
输入/输出数： 13
程序存储器容量： 896B（512 x 14）
程序存储器类型： OTP
RAM 容量： 80 x 8
电压 - 电源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
振荡器型： 外部
工作温度： 0°C ~ 70°C
封装/外壳： 20-SSOP（0.209"，5.30mm 宽）
包装： 带卷 (TR)
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 45
PIC16C55X
6.8
Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before SLEEP was executed (driving high, low, or hi-
impedance).
For lowest current consumption in this mode, all I/O
pins should be either at V
DD, or VSS, with no external
circuitry drawing current from the I/O pin. I/O pins that
are hi-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at V
DD or
V
SS for lowest current consumption. The contribution
from on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V
IHMC).
6.8.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
External RESET input on MCLR pin
2.
Watchdog Timer Wake-up (if WDT was enabled)
3.
Interrupt from RB0/INT pin or RB Port change
The first event will cause a device RESET. The two lat-
ter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD bit, which is set on power-up is cleared when
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have an NOP after the SLEEP instruction.
The WDT is cleared when the device wakes-up from
SLEEP, regardless of the source of wake-up.
FIGURE 6-14:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Note:
It should be noted that a RESET generated
by a WDT timeout does not drive MCLR
pin low.
Note:
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC
PC+1
PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency(2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2
0004h
0005h
Dummy cycle
T
OST(2)
PC+2
Note
1:
XT, HS or LP Oscillator mode assumed.
2:
T
OST = 1024TOSC (drawing not to scale). This delay will not be there for RC osc mode.
3:
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4:
CLKOUT is not available in these osc modes, but shown here for timing reference.
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