参数资料
型号: PIC16LC642T-04I/SO
厂商: Microchip Technology
文件页数: 58/125页
文件大小: 0K
描述: IC MCU OTP 4KX14 COMP 28SOIC
标准包装: 1,600
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 4MHz
外围设备: 欠压检测/复位,LED,POR,WDT
输入/输出数: 22
程序存储器容量: 7KB(4K x 14)
程序存储器类型: OTP
RAM 容量: 176 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 6 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
其它名称: PIC16LC642T-04ISO
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
38
M9999-040407-3.0
Queue Management Unit (QMU)
The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has
built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each
queue contains 4KB of memory for back-to-back, non-blocking frame transfer performance. It provides a group of control
registers for system control, frame status registers for current packet transmit/receive status, and interrupts to inform the
host of the real time TX/RX status.
Transmit Queue (TXQ) Frame Format
The frame format for the transmit queue is shown in the following Table 3. The first word contains the control information
for the frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data
follows. The packet data area holds the frame itself. It may or may not include the CRC checksum depending on whether
hardware CRC checksum generation is enabled.
Multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue memory,
thus avoiding overrun. For each transmitted frame, the transmit status information for the frame is located in the TXSR
register.
Packet Memory
Address Offset
Bit 15
Bit 0
2
nd Byte
1
st Byte
0
Control Word
2
Byte Count
4 - up
Packet Data
(maximum size is 1916)
Table 3. Transmit Queue Frame Format
Since multiple packets can be pipelined into the TX packet memory for transmit, the transmit status reflects the
status of the packet that is currently being transferred on the MAC interface (which may or may not be the last
queued packet in the TX queue).
The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must
be word aligned. Each control word corresponds to one TX packet. Table 4 gives the transmit control word bit
fields.
Bit
Description
15
TXIC Transmit Interrupt on Completion
When bit is set, the KSZ8862M sets the transmit interrupt after the present frame has been
transmitted.
14-10
Reserved
9-8
TXDPN Transmit Destination Port Number
When bit is set, this field indicates the destination port(s) where the packet is forwarded
from host system. Set bit 8 to indicate that port 1 is the destination port. Set bit 9 to
indicate that port 2 is the destination port.
Setting all ports to 1 causes the switch engine to broadcast the packet to both ports.
Setting all bits to 0 has no effect. The internal switch engine forwards the packets
according to the switching algorithm in its MAC lookup table.
7-6
Reserved
5-0
TXFID Transmit Frame ID
This field specifies the frame ID that is used to identify the frame and its associated status
information in the transmit status register TXSR[5:0].
Table 4. Transmit Control Word Bit Fields
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