参数资料
型号: PIC16LC712T-04I/SS
厂商: Microchip Technology
文件页数: 44/106页
文件大小: 0K
描述: IC MCU OTP 1KX14 A/D PWM 20SSOP
产品培训模块: Asynchronous Stimulus
标准包装: 1,600
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 4MHz
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 13
程序存储器容量: 1.75KB(1K x 14)
程序存储器类型: OTP
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2.5 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 20-SSOP(0.209",5.30mm 宽)
包装: 带卷 (TR)
其它名称: PIC16LC712T-04ISS
PIC16C712/716
DS41106B-page 40
2005 Microchip Technology Inc.
7.1
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RB3/CCP1. An event is defined as:
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
FIGURE 7-3:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
7.1.1
CCP PIN CONFIGURATION
In Capture mode, the CCP output must be disabled by
setting the TRISCCP<2> bit.
7.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
7.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in Operating mode.
7.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 7-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 7-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
Note:
If the RB3/CCP1 is configured as an out-
put by clearing the TRISCCP<2> bit, a
write to the DCCP bit can cause a capture
condition.
CCPR1H
CCPR1L
TMR1H
TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s
CCP1CON<3:0>
RB3/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
Pin
CLRF
CCP1CON
;Turn CCP module off
MOVLW
NEW_CAPT_PS
;Load the W reg with
; the new prescaler
; mode value and CCP ON
MOVWF
CCP1CON
;Load CCP1CON with this
; value
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