参数资料
型号: PIC16LC715T-04/SS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20
封装: 0.209 INCH, PLASTIC, SSOP-20
文件页数: 89/177页
文件大小: 1650K
代理商: PIC16LC715T-04/SS
1997 Microchip Technology Inc.
DS30272A-page 19
PIC16C71X
4.2.2.3
INTCON REGISTER
The INTCON Register is a readable and writable regis-
ter which contains various enable and ag bits for the
TMR0 register overow, RB Port change and External
RB0/INT pin interrupts.
Applicable Devices
710 71 711 715
Note:
Interrupt ag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
FIGURE 4-9:
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
R/W-x
GIE
ADIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7
bit0
bit 7:
GIE:(1) Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables A/D interrupt
0 = Disables A/D interrupt
bit 5:
T0IE: TMR0 Overow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overow Interrupt Flag bit
1 = TMR0 register has overowed (must be cleared in software)
0 = TMR0 register did not overow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note 1: For the PIC16C71, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may be uninten-
tionally re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. Refer to Section 8.5
for a detailed description.
Interrupt ag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ag bits are clear prior to
enabling an interrupt.
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