参数资料
型号: PIC16LC716-04/SS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20
封装: 0.209 INCH, PLASTIC, MO-150, SSOP-20
文件页数: 59/106页
文件大小: 1718K
代理商: PIC16LC716-04/SS
PIC16C712/716
DS41106B-page 54
2005 Microchip Technology Inc.
9.2.3
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit-to-unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used. Figure 9-4 shows how the R/C
combination is connected to the PIC16CXXX.
FIGURE 9-4:
RC OSCILLATOR MODE
9.3
Reset
The PIC16CXXX differentiates between various kinds
of Reset:
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset (during normal operation)
WDT Wake-up (during Sleep)
Brown-out Reset (BOR)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared
differently in different Reset situations as indicated in
Table 9-4. These bits are used in software to determine
the nature of the Reset. See Table 9-6 for a full
description of Reset states of all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 9-6.
The PICmicro microcontrollers have a MCLR noise
filter in the MCLR Reset path. The filter will detect and
ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
OSC2/CLKOUT
CEXT
REXT
PIC16C7XX
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values:
3 k
Ω ≤ REXT ≤ 100 kΩ
CEXT > 20pF
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