参数资料
型号: PIC17LC766T-08I/PT
厂商: Microchip Technology
文件页数: 46/159页
文件大小: 0K
描述: IC MCU OTP 16KX16 A/D PWM 80TQFP
标准包装: 1,200
系列: PIC® 17C
核心处理器: PIC
芯体尺寸: 8-位
速度: 8MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 66
程序存储器容量: 32KB(16K x 16)
程序存储器类型: OTP
RAM 容量: 902 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 16x10b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 80-TQFP
包装: 带卷 (TR)
其它名称: PIC17LC766T-08IPT
2000 Microchip Technology Inc.
DS30289B-page 21
PIC17C7XX
4.2
Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1 and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-8.
4.3
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then two cycles are required to complete the instruction
A fetch cycle begins with the program counter incre-
menting in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the Q2,
Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination write).
FIGURE 4-8:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 4-1:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC
PC+1
PC+2
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetched instruc-
tion is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h
Fetch 1
Execute 1
2. MOVWF PORTB
Fetch 2
Execute 2
3. CALL SUB_1
Fetch 3
Execute 3
4. BSF
PORTA, BIT3 (Forced NOP)
Fetch 4
Flush
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
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