参数资料
型号: PIC18F4331-I/ML
厂商: Microchip Technology
文件页数: 6/119页
文件大小: 0K
描述: IC PIC MCU FLASH 4KX16 44QFN
产品培训模块: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
标准包装: 45
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,电源控制 PWM,QEI,POR,PWM,WDT
输入/输出数: 36
程序存储器容量: 8KB(4K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 9x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-VQFN 裸露焊盘
包装: 管件
产品目录页面: 645 (CN2011-ZH PDF)
配用: XLT44QFN2-ND - SOCKET TRAN ICE 44QFN/40DIP
AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
I3-DB18F4431-ND - BOARD DAUGHTER ICEPIC3
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
103
M9999-100207-1.5
MIB (Management Information Base) Counters
The KSZ8842-PMQL/PMBL provides 32 MIB counters for port 1, port 2, and the host port. These counters are used to
monitor the port activity for network management. The MIB counters are formatted “per port” as shown in Table 8, and
“per all port dropped packet” as shown in Table 8.
Bit
Name
R/W
Description
Default
31
Overflow
RO
1 = counter overflow.
0 = no counter overflow.
0
30
Count valid
RO
1 = counter value is valid.
0 = counter value is not valid.
0
29-0
Counter values
RO
Counter value
0
Table 8. Format of Per Port MIB Counters
“Per Port” MIB counters are read using indirect memory access. The base address offsets and address ranges for both
Ethernet ports are:
Port 1, base address of the MIB counter is 0x00 and range is (0x00-0x1f) as shown in Table 9.
Port 2, base address of the MIB counter is 0x20 and range is (0x20-0x3f) as refer in Table 9.
Host port, base address of the MIB counter is 0x40 and range is (0x40-0x5f) as refer in Table 9.
Per Port MIB counters read/write functions use Access Control register IACR (0x04A0) bit 12. The base address offset
and address range for port 1 is 0x00 and range is (0x00-0x1F) that can be changed in register IACR (0x04A0) bits[9:0].
The data of MIB counters are from the Indirect Access data register IADR4 (0x04A8) and IADR5 (0x04AA) based on
Table 9.
Offset
Counter Name
Description
0x0
(base address)
RxLoPriorityByte
Rx lo-priority (default) octet count including bad packets
0x1
RxHiPriorityByte
Rx hi-priority octet count including bad packets
0x2
RxUndersizePkt
Rx undersize packets w/ good CRC
0x3
RxFragments
Rx fragment packets w/ bad CRC, symbol errors or alignment errors
0x4
RxOversize
Rx oversize packets w/ good CRC (max: 1536 or 1522 bytes)
0x5
RxJabbers
Rx packets longer than 1522 bytes w/ either CRC errors, alignment errors, or symbol
errors (depends on max packet size setting)
0x6
RxSymbolError
Rx packets w/ invalid data symbol and legal packet size.
0x7
RxCRCError
Rx packets within (64,1522) bytes w/ an integral number of bytes and a bad CRC
(upper limit depends on max packet size setting)
0x8
RxAlignmentError
Rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad CRC
(upper limit depends on max packet size setting)
0x9
RxControl8808Pkts
Number of MAC control frames received by a port with 88-08h in EtherType field
0xA
RxPausePkts
Number of PAUSE frames received by a port. PAUSE frame is qualified with
EtherType (88-08h), DA, control opcode (00-01), data length (64B min), and a valid
CRC
0xB
RxBroadcast
Rx good broadcast packets (not including error broadcast packets or valid multicast
packets)
0xC
RxMulticast
Rx good multicast packets (not including MAC control frames, error multicast packets
or valid broadcast packets)
0xD
RxUnicast
Rx good unicast packets
0xE
Rx64Octets
Total Rx packets (bad packets included) that were 64 octets in length
0xF
Rx65to127Octets
Total Rx packets (bad packets included) that are between 65 and 127 octets in length
0x10
Rx128to255Octets
Total Rx packets (bad packets included) that are between 128 and 255 octets in
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