PIC18FXX2
DS39564C-page 46
2006 Microchip Technology Inc.
TABLE 4-2:
REGISTER FILE SUMMARY
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
TOSU
—
Top-of-Stack upper Byte (TOS<20:16>)
---0 0000
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
STKPTR
STKFUL
STKUNF
—
Return Stack Pointer
00-0 0000
PCLATU
—
Holding Register for PC<20:16>
---0 0000
PCLATH
Holding Register for PC<15:8>
0000 0000
PCL
PC Low Byte (PC<7:0>)
0000 0000
TBLPTRU
—
—bit21(2)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
TABLAT
Program Memory Table Latch
0000 0000
PRODH
Product Register High Byte
xxxx xxxx
PRODL
Product Register Low Byte
xxxx xxxx
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
—TMR0IP
—RBIP
1111 -1-1
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
11-0 0-00
INDF0
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
n/a
POSTINC0
Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)
n/a
POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)
n/a
PREINC0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)
n/a
PLUSW0
Uses contents of FSR0 to address data memory - value of FSR0 (not a physical register).
Offset by value in WREG.
n/a
FSR0H
—
Indirect Data Memory Address Pointer 0 High Byte ---- 0000
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
WREG
Working Register
xxxx xxxx
n/a
INDF1
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
n/a
POSTINC1
Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)
n/a
POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)
n/a
PREINC1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
n/a
PLUSW1
Uses contents of FSR1 to address data memory - value of FSR1 (not a physical register).
Offset by value in WREG.
n/a
FSR1H
—
Indirect Data Memory Address Pointer 1 High Byte ---- 0000
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
BSR
—
Bank Select Register
---- 0000
INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
n/a
POSTINC2
Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)
n/a
POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)
n/a
PREINC2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)
n/a
PLUSW2
Uses contents of FSR2 to address data memory - value of FSR2 (not a physical register).
Offset by value in WREG.
n/a
FSR2H
—
Indirect Data Memory Address Pointer 2 High Byte ---- 0000
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
STATUS
—
—N
OV
Z
DC
C
---x xxxx
TMR0H
Timer0 Register High Byte
0000 0000
TMR0L
Timer0 Register Low Byte
xxxx xxxx
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
Legend:
x
= unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes.
2:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
3:
These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear.