参数资料
型号: PIC18F44J10T-I/PT
厂商: Microchip Technology
文件页数: 44/80页
文件大小: 0K
描述: IC PIC MCU FLASH 8KX16 44TQFP
产品培训模块: Asynchronous Stimulus
PIC18 J Series MCU Overview
标准包装: 1
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 16KB(8K x 16)
程序存储器类型: 闪存
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 13x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-TQFP
包装: 剪切带 (CT)
配用: AC162074-ND - HEADER INTRFC MPLAB ICD2 44TQFP
MA180013-ND - MODULE PLUG-IN 18F45J10 44TQFP
AC162067-ND - HEADER INTRFC MPLAB ICD2 40/28P
AC164330-ND - MODULE SKT FOR 44TQFP 18F45J10
其它名称: PIC18F44J10T-I/PTCT
PIC16F8X
1998 Microchip Technology Inc.
DS30430C-page 49
FIGURE 8-17: INT PIN INTERRUPT TIMING
8.9.1
INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION_REG<6>) is set,
or falling, if INTEDG bit is clear. When a valid edge
appears
on
the
RB0/INT
pin,
the
INTF
bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software via the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 8.12) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches
to the interrupt vector
following wake-up.
8.9.2
TMR0 INTERRUPT
An overflow (FFh
→ 00h) in TMR0 will set flag bit T0IF
(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
8.9.3
PORT RB INTERRUPT
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
Interrupt Latency
PC
PC+1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC+1)
Inst (PC-1)
Inst (0004h)
Dummy Cycle
Inst (PC)
1
4
5
1
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
2
3
Note 1: For a change on the I/O pin to be
recognized, the pulse width must be at
least TCY wide.
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